From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 16 Jun 2019 05:41:42 +0000 (-0700)
Subject: Read init from outputs
X-Git-Tag: working-ls180~881^2^2~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d1185b835e16cc0613aa7a31e810dd6da69599f;p=yosys.git

Read init from outputs
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index d2657c9da..5a6db8481 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -927,6 +927,10 @@ void AigerReader::post_process()
 					}
 				}
 				log_debug(" -> %s\n", log_id(wire));
+				int init;
+				mf >> init;
+				if (init < 2)
+					wire->attributes["\\init"] = init;
 			}
 			else if (type == "box") {
 				RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));