From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 27 Dec 2021 04:35:17 +0000 (+0000)
Subject: quick attempt to fix test_decoder_gas.py (did not work)
X-Git-Tag: sv_maxu_works-initial~594
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d1dac4e342f7f3e0e87d96fcb556b58a659db1e;p=openpower-isa.git

quick attempt to fix test_decoder_gas.py (did not work)
---

diff --git a/src/openpower/decoder/test/test_decoder_gas.py b/src/openpower/decoder/test/test_decoder_gas.py
index a8951fa2..b5b9ae2e 100644
--- a/src/openpower/decoder/test/test_decoder_gas.py
+++ b/src/openpower/decoder/test/test_decoder_gas.py
@@ -2,7 +2,7 @@ from nmigen import Module, Signal
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
-from nmutil.sim_tmp_alternative import Simulator, Delay
+from nmutil.sim_tmp_alternative import Simulator, Delay, Settle
 
 from nmutil.formaltest import FHDLTestCase
 import unittest
@@ -222,9 +222,9 @@ class CmpRegOp:
         r2sel = yield pdecode2.e.read_reg2.data
         crsel = yield pdecode2.dec.BF
 
-        assert(r1sel == self.r1.num)
-        assert(r2sel == self.r2.num)
-        assert(crsel == self.cr.num)
+        assert r1sel == self.r1.num, "r1sel %d != r1 %d" % (r1sel, self.r1.num)
+        assert r2sel == self.r2.num, "r2sel %d != r2 %d" % (r2sel, self.r2.num)
+        assert crsel == self.cr.num, "crsel %d != cr %d" % (crsel, self.cr.num)
 
 
 class RotateOp:
@@ -465,7 +465,7 @@ class DecoderTestCase(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(mode)  # little / big?
                     yield instruction.eq(ibin)            # raw binary instr.
-                    yield Delay(1e-6)
+                    yield Settle()
 
                     yield from checker.check_results(pdecode2)
 
@@ -473,7 +473,7 @@ class DecoderTestCase(FHDLTestCase):
         ports = pdecode2.ports()
         print(ports)
         with sim.write_vcd("%s.vcd" % name, "%s.gtkw" % name,
-                           traces=ports):
+                           traces=[]):
             sim.run()
 
     def test_reg_reg(self):