From: lkcl <lkcl@web>
Date: Thu, 8 Sep 2022 18:30:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~590
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d3267a0c2663c7ba2b6344cc3b675f7a490a2f9;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 1e501915c..a672765bb 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -32,7 +32,8 @@ the **Scalar** Power ISA before Simple-V may orthogonally Vectorise them.
 Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER
 Stakeholder, is to bring to market mass-volume general-purpose compute
 processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT
-desktop chromebook netbook smartphone laptop markets, Simple-V has to
+desktop chromebook netbook smartphone laptop markets, performance-leveraged
+by Simple-V.  Simple-V thus has to
 be accompanied by corresponding **Scalar** instructions that bring the
 **Scalar** Power ISA up-to-date.  These include IEEE754 Transcendentals
 AV cryptographic Biginteger and bitmanipulation operations that ARM