From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 17:18:08 +0000 (-0800)
Subject: abc9_ops: assert on $specify2 properties
X-Git-Tag: working-ls180~780^2~43
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d6603792dbd36ccb572403815b78121a7ad80e8;p=yosys.git

abc9_ops: assert on $specify2 properties
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d08c42e3b..52beae421 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -572,7 +572,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 				continue;
 			log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
 			log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
+			SigBit s = cell->getPort(ID(SRC));
 			SigBit d = cell->getPort(ID(DST));
+			log_assert(s.wire->port_input);
+			log_assert(d.wire->port_output);
 			if (o == SigBit())
 				o = d;
 			else