From: lkcl <lkcl@web>
Date: Sat, 1 May 2021 10:11:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1000
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d679b9a8830f327ab039ee9e24bdbd66832ea04;p=libreriscv.git

---

diff --git a/index.mdwn b/index.mdwn
index 8045a8414..317b1aae6 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -126,6 +126,7 @@ step you will have needed to install yosys:
     git clone https://git.libre-soc.org/git/nmigen.git
     git clone https://git.libre-soc.org/git/nmigen-soc.git
     git clone https://git.libre-soc.org/git/nmutil.git
+    git clone https://git.libre-soc.org/git/openpower-isa.git
     git clone https://git.libre-soc.org/git/c4m-jtag.git
     git clone https://git.libre-soc.org/git/ieee754fpu.git
     git clone https://git.libre-soc.org/git/soc.git
@@ -133,8 +134,9 @@ step you will have needed to install yosys:
     cd nmigen; python setup.py develop; cd ..
     cd nmigen-soc; python setup.py develop; cd ..
     cd c4m-jtag; python setup.py develop; cd ..
-    cd nmutil; make install; cd ..
-    cd ieee754fpu; make install; cd ..
+    cd nmutil; make develop; cd ..
+    cd openpower-isa; make develop; cd ..
+    cd ieee754fpu; make develop; cd ..
     cd soc; make gitupdate; make develop
     
     python3 src/soc/decoder/power_decoder.py