From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 5 Jun 2021 17:34:32 +0000 (+0000)
Subject: whoops, fake pll/mem need vss/vdd
X-Git-Tag: LS180_RC3~27^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d6f1c59e70df22b604249e91cb5ea78f2c067db;p=soclayout.git

whoops, fake pll/mem need vss/vdd
---

diff --git a/experiments10_verilog/pll.py b/experiments10_verilog/pll.py
index 56163ae..03a6ccc 100644
--- a/experiments10_verilog/pll.py
+++ b/experiments10_verilog/pll.py
@@ -224,7 +224,11 @@ def _load():
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
             'out_v': Net.create(cell, 'out_v'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vdd'].setGlobal(True)
+        nets['vss'].setGlobal(True)
 
         # set net directions
         nets['ref_v'].setDirection( Net.Direction.IN )
diff --git a/experiments9/LibreSOCMem.py b/experiments9/LibreSOCMem.py
index 8489df4..4c4753d 100644
--- a/experiments9/LibreSOCMem.py
+++ b/experiments9/LibreSOCMem.py
@@ -219,9 +219,11 @@ def _load():
         nets = {
             '*': Net.create(cell, '*'),
             'clk': Net.create(cell, 'clk'),
-            #'vdd': Net.create(cell, 'vdd'),
-            #'vss': Net.create(cell, 'vss'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vss'].setGlobal(True)
+        nets['vdd'].setGlobal(True)
         for name, qty in (('a', 9),
                           ('d', 64),
                           ('q', 64),
diff --git a/experiments9/pll.py b/experiments9/pll.py
index 56163ae..03a6ccc 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -224,7 +224,11 @@ def _load():
             'a1': Net.create(cell, 'a1'),
             'vco_test_ana': Net.create(cell, 'vco_test_ana'),
             'out_v': Net.create(cell, 'out_v'),
+            'vdd': Net.create(cell, 'vdd'),
+            'vss': Net.create(cell, 'vss'),
         }
+        nets['vdd'].setGlobal(True)
+        nets['vss'].setGlobal(True)
 
         # set net directions
         nets['ref_v'].setDirection( Net.Direction.IN )