From: whitequark <whitequark@whitequark.org>
Date: Sun, 27 Jan 2019 00:21:31 +0000 (+0000)
Subject: write_verilog: write $tribuf cell as ternary.
X-Git-Tag: yosys-0.9~320^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d7925ad9f7840d5269b84d053ae808f36ccf762;p=yosys.git

write_verilog: write $tribuf cell as ternary.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627..54281e32e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -789,6 +789,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$tribuf")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(" ? ");
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
+		return true;
+	}
+
 	if (cell->type == "$slice")
 	{
 		f << stringf("%s" "assign ", indent.c_str());