From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 11 Sep 2015 22:13:26 +0000 (-0700)
Subject: Initialize mstatus.prv1/prv2 to U, not S
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d9330919b8cb451cb5dccf689fe171fe298749a;p=riscv-isa-sim.git

Initialize mstatus.prv1/prv2 to U, not S

This doesn't really matter, but it matches Rocket.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index e14859e..962e9cd 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -107,8 +107,8 @@ void state_t::reset()
 {
   memset(this, 0, sizeof(*this));
   mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
-  mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
-  mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
+  mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_U);
+  mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_U);
   pc = DEFAULT_MTVEC + 0x100;
   load_reservation = -1;
 }