From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 26 Sep 2018 15:22:29 +0000 (+0100)
Subject: whoops vectorop has to be |= not &= to accumulate "true"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d98b17f95fd2616f6ec21d39a3a9f91a993de2d;p=riscv-isa-sim.git

whoops vectorop has to be |= not &= to accumulate "true"
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index de09f50..3163a34 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -22,29 +22,29 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   // really could do with a macro for-loop here... oh well...
   // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
 #ifdef USING_RD
-  vectorop &= check_reg(true, s_insn.rd());
+  vectorop |= check_reg(true, s_insn.rd());
 #endif
 #ifdef USING_RS1
-  vectorop &= check_reg(true, s_insn.rs1());
+  vectorop |= check_reg(true, s_insn.rs1());
 #endif
 #ifdef USING_RS2
-  vectorop &= check_reg(true, s_insn.rs2());
+  vectorop |= check_reg(true, s_insn.rs2());
 #endif
 #ifdef USING_RS2
-  vectorop &= check_reg(true, s_insn.rs3());
+  vectorop |= check_reg(true, s_insn.rs3());
 #endif
   // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
 #ifdef USING_FRD
-  vectorop &= check_reg(false, s_insn.frd());
+  vectorop |= check_reg(false, s_insn.frd());
 #endif
 #ifdef USING_FRS1
-  vectorop &= check_reg(false, s_insn.frs1());
+  vectorop |= check_reg(false, s_insn.frs1());
 #endif
 #ifdef USING_FRS2
-  vectorop &= check_reg(false, s_insn.rs2());
+  vectorop |= check_reg(false, s_insn.rs2());
 #endif
 #ifdef USING_FRS2
-  vectorop &= check_reg(false, s_insn.rs3());
+  vectorop |= check_reg(false, s_insn.rs3());
 #endif
 
   // if vectorop is set, one of the regs is not a scalar,