From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 21 Apr 2016 07:39:21 +0000 (+0200)
Subject: use new Record.connect omit parameter (replace leave_out)
X-Git-Tag: 24jan2021_ls180~1966
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d98be0997f07a8f11cfa234d785d79adea02d92;p=litex.git

use new Record.connect omit parameter (replace leave_out)
---

diff --git a/litex/soc/cores/sdram/phy/s6ddrphy.py b/litex/soc/cores/sdram/phy/s6ddrphy.py
index 71148bb6..8fe77a53 100644
--- a/litex/soc/cores/sdram/phy/s6ddrphy.py
+++ b/litex/soc/cores/sdram/phy/s6ddrphy.py
@@ -451,14 +451,14 @@ class S6QuarterRateDDRPHY(Module):
         # DFI adaptation
 
         # Commands and writes
-        dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"])
+        dfi_omit = set(["rddata", "rddata_valid", "wrdata_en"])
         self.comb += [
             If(~phase_sel,
-                self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
-                self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
+                self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
+                self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
             ).Else(
-                self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
-                self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
+                self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], omit=dfi_omit),
+                self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], omit=dfi_omit),
             ),
         ]
         wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel
diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index a12562fd..63f4c1f6 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -276,7 +276,7 @@ class Converter(Module):
         else:
             self.source = Endpoint([("data", nbits_to)])
             self.comb += converter.source.connect(self.source,
-                            leave_out=set(["valid_token_count"]))
+                            omit=set(["valid_token_count"]))
 
 
 class StrideConverter(Module):