From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 10 Dec 2021 20:34:23 +0000 (-0800)
Subject: change ternlogi to not have Rc field
X-Git-Tag: sv_maxu_works-initial~641
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3d9d4a0864e4e5d4ab6dc13348ec3289748285d6;p=openpower-isa.git

change ternlogi to not have Rc field
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
index daa6e670..650d56e9 100644
--- a/openpower/isa/bitmanip.mdwn
+++ b/openpower/isa/bitmanip.mdwn
@@ -5,8 +5,7 @@
 
 TLI-Form
 
-* ternlogi RT, RA, RB, TLI (Rc=0)
-* ternlogi. RT, RA, RB, TLI (Rc=1)
+* ternlogi RT, RA, RB, TLI
 
 Pseudo-code:
 
@@ -21,4 +20,4 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    CR0                    (if Rc=1)
+    None
diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index bf9b055c..aadf9f5d 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -284,8 +284,8 @@
    | PO   | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO    | / |
 
 # 1.6.34 TLI-FORM
-   |0   |6   |11   |16   |21   |29  |31 |
-   | PO | RT |  RA |  RB | TLI | XO |Rc |
+   |0   |6   |11   |16   |21   |29  |
+   | PO | RT |  RA |  RB | TLI | XO |
 
 # 1.6.28 Instruction Fields
     A (6)
@@ -956,12 +956,9 @@
     XO (27:30)
         Extended opcode field.
         Formats: MDS
-    XO (29:30)
-        Extended opcode field.
-        Formats: TLI
     XO (29:31)
         Extended opcode field.
-        Formats: DQ
+        Formats: DQ, TLI
     XO (30)
         Extended opcode field.
         Formats: SC
diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv
index ec8d671d..26d7c8b0 100644
--- a/openpower/isatables/minor_5.csv
+++ b/openpower/isatables/minor_5.csv
@@ -1,2 +1,2 @@
 opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2
---------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+--------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 944d0324..f2a5aded 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1233,7 +1233,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = 'ffadds'
 
-        if asmop == 'ternlogi' or asmop == 'ternlogi.':
+        if asmop == 'ternlogi':
             illegal = False
             ins_name = asmop
 
diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index 8b112094..0c73d016 100644
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -12,7 +12,7 @@ def hash_256(v):
 
 
 class BitManipTestCase(TestAccumulatorBase):
-    def do_case_ternlogi(self, rt_v, ra_v, rb_v, imm, rc):
+    def do_case_ternlogi(self, rt_v, ra_v, rb_v, imm):
         po = 5
         xo = 0
         rt = 3
@@ -23,9 +23,8 @@ class BitManipTestCase(TestAccumulatorBase):
         instr = (instr << 5) | ra
         instr = (instr << 5) | rb
         instr = (instr << 8) | imm
-        instr = (instr << 2) | xo
-        instr = (instr << 1) | rc
-        asm = f"ternlogi{'.' * rc} {rt}, {ra}, {rb}, {imm}"
+        instr = (instr << 3) | xo
+        asm = f"ternlogi {rt}, {ra}, {rb}, {imm}"
         lst = [f".4byte {hex(instr)} # {asm}"]
         initial_regs = [0] * 32
         initial_regs[3] = rt_v % 2 ** 64
@@ -36,16 +35,15 @@ class BitManipTestCase(TestAccumulatorBase):
     def case_ternlogi_0(self):
         self.do_case_ternlogi(0x8000_0000_FFFF_0000,
                               0x8000_0000_FF00_FF00,
-                              0x8000_0000_F0F0_F0F0, 0x80, rc=1)
+                              0x8000_0000_F0F0_F0F0, 0x80)
 
     def case_ternlogi_FF(self):
-        self.do_case_ternlogi(0, 0, 0, 0xFF, rc=1)
+        self.do_case_ternlogi(0, 0, 0, 0xFF)
 
-    @skip_case
     def case_ternlogi_random(self):
         for i in range(100):
             imm = hash_256(f"ternlogi imm {i}") & 0xFF
             rt_v = hash_256(f"ternlogi rt {i}") % 2 ** 64
             ra_v = hash_256(f"ternlogi ra {i}") % 2 ** 64
             rb_v = hash_256(f"ternlogi rb {i}") % 2 ** 64
-            self.do_case_ternlogi(rt_v, ra_v, rb_v, imm, rc=1)
+            self.do_case_ternlogi(rt_v, ra_v, rb_v, imm)