From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Nov 2020 17:47:46 +0000 (+0000)
Subject: reduce clkcsel ls180 width (2 pins), rename pll_18 signal
X-Git-Tag: 24jan2021_ls180~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3dce9e7342e15c491ecc0bdb3acf90e2987dd0b3;p=soc.git

reduce clkcsel ls180 width (2 pins), rename pll_18 signal
---

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index 8594f91e..2dd8f714 100644
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -16,9 +16,9 @@ class DummyPLL(Elaboratable):
         m = Module()
         m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
         # just get something, stops yosys destroying (optimising) these out
-        m.d.comb += self.pll_18_o.eq(self.clk_24_i)
         with m.If(self.clk_sel_i == Const(0, 2)):
             m.d.comb += self.pll_lck_o.eq(self.clk_24_i)
+            m.d.comb += self.pll_18_o.eq(~self.clk_24_i)
 
         return m
 
diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 12112b66..1c521106 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -240,7 +240,7 @@ class LibreSoC(CPU):
         # add clock select, pll output
         if variant == "ls180":
             self.pll_18_o = Signal()
-            self.clk_sel = Signal(3)
+            self.clk_sel = Signal(2)
             self.pll_lck_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 3eb9abeb..98c117f6 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -49,7 +49,7 @@ def io():
         # CLK/RST: 2 pins
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
-        ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
+        ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
         ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5a62fdcd..d662dff4 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -463,6 +463,8 @@ class TestIssuer(Elaboratable):
 
         # PLL direct clock or not
         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+        if self.pll_en:
+            self.pll_18_o = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
@@ -488,6 +490,9 @@ class TestIssuer(Elaboratable):
             # wire up external 24mhz to PLL
             comb += pll.clk_24_i.eq(ClockSignal())
 
+            # output 18 mhz PLL test signal
+            comb += self.pll_18_o.eq(pll.pll_18_o)
+
             # now wire up ResetSignals.  don't mind them being in this domain
             pll_rst = ResetSignal("pllclk")
             comb += pll_rst.eq(ResetSignal())
@@ -512,7 +517,7 @@ class TestIssuer(Elaboratable):
         ports.append(ResetSignal())
         if self.pll_en:
             ports.append(self.pll.clk_sel_i)
-            ports.append(self.pll.pll_18_o)
+            ports.append(self.pll_18_o)
             ports.append(self.pll.pll_lck_o)
         return ports