From: lkcl Date: Fri, 25 Dec 2020 17:37:04 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~897 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3dd2c2512e455057972e91a8dcced345439fdc0d;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 291fad549..fe50bc7fa 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -186,7 +186,7 @@ as if this were a straight OpenPOWER v3.0B non-augmented instruction. Single Predication therefore provides several modes traditionally seen in Vector ISAs: -* the predicate may be set as a single bit, the sources are scalar and the destination a vector: this gives VINSERT (VINDEX) behaviour. +* VINSERT: the predicate may be set as a single bit, the sources are scalar and the destination a vector. * VSPLAT (result broadcasting) is provided by making the sources scalar and the destination a vector, and having no predicate set or having multiple bits set. * VSELECT is provided by setting up (at least one of) the sources as a vector, using a single bit in olthe predicate, and the destination as a scalar.