From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Feb 2020 16:13:59 +0000 (+0000)
Subject: hdl.dsl: reject name mismatch in `m.domains.<name> +=`.
X-Git-Tag: v0.2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3df429703c4067baf7718c00cb21d733d4454492;p=nmigen.git

hdl.dsl: reject name mismatch in `m.domains.<name> +=`.

This would violate invariants later in the elaboration process.

Fixes #282.
---

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index aaecd9c..96f1923 100644
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -118,6 +118,10 @@ class _ModuleBuilderDomainSet:
         if not isinstance(domain, ClockDomain):
             raise TypeError("Only clock domains may be added to `m.domains`, not {!r}"
                             .format(domain))
+        if domain.name != name:
+            raise NameError("Clock domain name {!r} must match name in `m.domains.{} += ...` "
+                            "syntax"
+                            .format(domain.name, name))
         self._builder._add_domain(domain)
 
 
diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index 959c6e5..9b3a91d 100644
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -716,6 +716,12 @@ class DSLTestCase(FHDLTestCase):
                 msg="Only clock domains may be added to `m.domains`, not 1"):
             m.domains += 1
 
+    def test_domain_add_wrong_name(self):
+        m = Module()
+        with self.assertRaises(NameError,
+                msg="Clock domain name 'bar' must match name in `m.domains.foo += ...` syntax"):
+            m.domains.foo = ClockDomain("bar")
+
     def test_lower(self):
         m1 = Module()
         m1.d.comb += self.c1.eq(self.s1)