From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 7 Jan 2020 00:22:22 +0000 (-0800)
Subject: Add testcase from #1459
X-Git-Tag: working-ls180~873^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3df869cc7cb6bd0afc2850bdcd5ce0409a36d53c;p=yosys.git

Add testcase from #1459
---

diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys
new file mode 100644
index 000000000..1142ae0b5
--- /dev/null
+++ b/tests/arch/ecp5/bug1459.ys
@@ -0,0 +1,25 @@
+read_verilog <<EOT
+module register_file(
+    input wire clk,
+    input wire write_enable,
+    input wire [63:0] write_data,
+    input wire [4:0] write_reg,
+    input wire [4:0] read1_reg,
+    output reg [63:0] read1_data,
+    );
+
+    reg [63:0] registers[0:31];
+
+    always @(posedge clk) begin
+      if (write_enable == 1'b1) begin
+        registers[write_reg] <= write_data;
+      end
+    end
+
+    always @(all) begin
+      read1_data <= registers[read1_reg];
+    end
+endmodule
+EOT
+
+synth_ecp5 -abc9