From: Luke Kenneth Casson Leighton Date: Sun, 26 Jul 2020 10:11:25 +0000 (+0100) Subject: move run_test_program to base class and rename to "add_case" X-Git-Tag: semi_working_ecp5~533 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e018e4f2dbc25a3420aeb1a41d0bce410107262;p=soc.git move run_test_program to base class and rename to "add_case" --- diff --git a/src/soc/fu/div/test/test_all_pipe_caller.py b/src/soc/fu/div/test/test_all_pipe_caller.py index c826de00..319f1ef8 100644 --- a/src/soc/fu/div/test/test_all_pipe_caller.py +++ b/src/soc/fu/div/test/test_all_pipe_caller.py @@ -11,12 +11,7 @@ from soc.fu.div.pipe_data import DivPipeKind class DivTestLong(TestAccumulatorBase): - def run_test_program(self, prog, initial_regs=None, initial_sprs=None): - test_name = inspect.stack()[1][3] # name of caller of this function - tc = TestCase(prog, test_name, initial_regs, initial_sprs) - self.test_data.append(tc) - - def case__all(self): + def case_all(self): instrs = [] for width in ("w", "d"): for sign in ("", "u"): @@ -48,7 +43,7 @@ class DivTestLong(TestAccumulatorBase): initial_regs[2] = rb # use "with" so as to close the files used with Program(l, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) if __name__ == "__main__": diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index bfaa6560..6b02d0d9 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -1,4 +1,3 @@ -import inspect import random import unittest from soc.simulator.program import Program @@ -13,11 +12,6 @@ from soc.fu.div.test.runner import (log_rand, get_cu_inputs, class DivTestCases(TestAccumulatorBase): - def run_test_program(self, prog, initial_regs=None, initial_sprs=None): - test_name = inspect.stack()[1][3] # name of caller of this function - tc = TestCase(prog, test_name, initial_regs, initial_sprs) - self.test_data.append(tc) - def case_0_regression(self): for i in range(40): lst = ["divwo 3, 1, 2"] @@ -25,7 +19,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0xbc716835f32ac00c initial_regs[2] = 0xcdf69a7f7042db66 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_1_regression(self): lst = ["divwo 3, 1, 2"] @@ -33,7 +27,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x10000000000000000-4 initial_regs[2] = 0x10000000000000000-2 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_2_regression(self): lst = ["divwo 3, 1, 2"] @@ -41,7 +35,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0xffffffffffff9321 initial_regs[2] = 0xffffffffffff7012 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_3_regression(self): lst = ["divwo. 3, 1, 2"] @@ -49,7 +43,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x1b8e32f2458746af initial_regs[2] = 0x6b8aee2ccf7d62e9 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_4_regression(self): lst = ["divw 3, 1, 2"] @@ -57,7 +51,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x1c4e6c2f3aa4a05c initial_regs[2] = 0xe730c2eed6cc8dd7 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_5_regression(self): lst = ["divw 3, 1, 2", @@ -68,7 +62,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[4] = 0x1b8e32f2458746af initial_regs[5] = 0x6b8aee2ccf7d62e9 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_6_regression(self): # CR0 not getting set properly for this one @@ -80,7 +74,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x61c1cc3b80f2a6af initial_regs[2] = 0x9dc66a7622c32bc0 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_7_regression(self): # https://bugs.libre-soc.org/show_bug.cgi?id=425 @@ -89,7 +83,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0xf1791627e05e8096 initial_regs[2] = 0xffc868bf4573da0b with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_8_fsm_regression(self): # FSM result is "36" not 6 lst = ["divwu. 3, 1, 2"] @@ -97,7 +91,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 18 initial_regs[2] = 3 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11 lst = ["divw. 3, 1, 2"] @@ -105,7 +99,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 1 initial_regs[2] = 0 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_divw_by_zero_1(self): lst = ["divw. 3, 1, 2"] @@ -113,7 +107,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x1 initial_regs[2] = 0x0 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_divw_overflow2(self): lst = ["divw. 3, 1, 2"] @@ -121,7 +115,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x80000000 initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_divw_overflow3(self): lst = ["divw. 3, 1, 2"] @@ -129,7 +123,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x80000000 initial_regs[2] = 0xffffffff with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_divwuo_regression_1(self): lst = ["divwuo. 3, 1, 2"] @@ -137,7 +131,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x7591a398c4e32b68 initial_regs[2] = 0x48674ab432867d69 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_divwuo_1(self): lst = ["divwuo. 3, 1, 2"] @@ -145,7 +139,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = 0x50 initial_regs[2] = 0x2 with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_rand_divwu(self): insns = ["divwu", "divwu.", "divwuo", "divwuo."] @@ -156,7 +150,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = log_rand(32) initial_regs[2] = log_rand(32) with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) def case_rand_divw(self): insns = ["divw", "divw.", "divwo", "divwo."] @@ -167,7 +161,7 @@ class DivTestCases(TestAccumulatorBase): initial_regs[1] = log_rand(32) initial_regs[2] = log_rand(32) with Program(lst, bigendian) as prog: - self.run_test_program(prog, initial_regs) + self.add_case(prog, initial_regs) if __name__ == "__main__": diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index c7f87dd9..b4bceb1b 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -3,6 +3,7 @@ Bugreports: * https://bugs.libre-soc.org/show_bug.cgi?id=361 """ +import inspect from soc.decoder.power_enums import XER_bits, CryIn, spr_dict from soc.regfile.util import fast_reg_to_spr # HACK! from soc.regfile.regfiles import FastRegs @@ -18,6 +19,11 @@ class TestAccumulatorBase: if n.startswith("case_") and callable(v): v(self) + def add_case(self, prog, initial_regs=None, initial_sprs=None): + test_name = inspect.stack()[1][3] # name of caller of this function + tc = TestCase(prog, test_name, initial_regs, initial_sprs) + self.test_data.append(tc) + class TestCase: def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,