From: Michael Neuling Date: Mon, 22 Jun 2020 03:09:09 +0000 (+1000) Subject: Fix building with yosys/nextpnr X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e0ac8c94c6ee828e5dffcb7ba6b8f6174cb3eb1;p=microwatt.git Fix building with yosys/nextpnr Add --no-formal so that asserts are removed by yosys as nextpnr doesn't like them. This was suggested by @tgingold here: https://github.com/YosysHQ/yosys/issues/2068#issuecomment-644545863 Signed-off-by: Michael Neuling --- diff --git a/Makefile b/Makefile index 96631e7..b4dab31 100644 --- a/Makefile +++ b/Makefile @@ -175,10 +175,10 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \ synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm) microwatt.json: $(synth_files) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@" microwatt.v: $(synth_files) - $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" + $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@" # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c