From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 02:00:17 +0000 (+0000)
Subject: starting to put in addr_mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e0d4e588af444ea3a5b44f3f147627ff204de8b;p=riscv-isa-sim.git

starting to put in addr_mode
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 3e8f389..1e2c542 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -153,15 +153,18 @@ reg_t sv_proc_t::READ_REG(reg_spec_t const& spec, sv_reg_t const& imm,
     int shift = 0;
     int offs = 0;
     if (spec.offset != NULL && spec.reg != 2) { // XXX HACK on spec.reg != 2
-        int nbytes = xlen / bitwidth;
+        int nbytes = width / bitwidth;
+        if (nbytes == 0) {
+            nbytes = 1;
+        }
         offs = *spec.offset;
         shift = offs % nbytes;
         offs /= nbytes;
         reg += offs;
     }
     uint64_t data = _insn->p->get_state()->XPR[reg];
-    uint64_t ndata = data;
-    if (xlen != bitwidth)
+    uint64_t ndata = data; // + (int64_t)imm;
+    if (((uint64_t)xlen) != ((uint64_t)bitwidth))
     {
         ndata = data >> (shift*bitwidth); // gets element within the reg-block
         ndata &= ((1UL<<bitwidth)-1UL); // masks off the right bits