From: Richard Sandiford Date: Tue, 13 Aug 2019 09:38:39 +0000 (+0000) Subject: [AArch64] Make the complete mnemonic X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e2751ce5591dc8f3b5f4ffd3dacf0fb8f789395;p=gcc.git [AArch64] Make the complete mnemonic The Advanced SIMD and SVE permute patterns both split the permute operation into a base name and a hilo suffix. That works well, but it means that for "@" patterns, we need to pass the permute code twice, once for the base name and once for the suffix. Having a unified name avoids that and also makes the definitions slightly simpler. 2019-08-13 Richard Sandiford gcc/ * config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix. (perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*. * config/aarch64/aarch64-simd.md (aarch64_): Rename to.. (aarch64_): ...this and remove perm_hilo from the asm template. * config/aarch64/aarch64-sve.md (aarch64_): Rename to.. (aarch64_): ...this and remove perm_hilo from the asm template. (aarch64_): Rename to.. (aarch64_): ...this and remove perm_hilo from the asm template. * config/aarch64/aarch64-simd-builtins.def: Update comment. From-SVN: r274366 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cc06158cf4e..8562f53e678 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2019-08-13 Richard Sandiford + + * config/aarch64/iterators.md (perm_insn): Include the "1"/"2" suffix. + (perm_hilo): Remove UNSPEC_ZIP*, UNSEPC_TRN* and UNSPEC_UZP*. + * config/aarch64/aarch64-simd.md + (aarch64_): Rename to.. + (aarch64_): ...this and remove perm_hilo + from the asm template. + * config/aarch64/aarch64-sve.md + (aarch64_): Rename to.. + (aarch64_): ...this and remove perm_hilo + from the asm template. + (aarch64_): Rename to.. + (aarch64_): ...this and remove perm_hilo + from the asm template. + * config/aarch64/aarch64-simd-builtins.def: Update comment. + 2019-08-13 Martin Liska * value-prof.c (gimple_ic_transform): Add new line. diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 17bb0c4869b..01518fec69b 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -424,7 +424,7 @@ BUILTIN_VB (UNOP, rbit, 0) /* Implemented by - aarch64_. */ + aarch64_. */ BUILTIN_VALL (BINOP, zip1, 0) BUILTIN_VALL (BINOP, zip2, 0) BUILTIN_VALL (BINOP, uzp1, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c6ccc99a2aa..e33a00967a9 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5781,13 +5781,13 @@ ;; This instruction's pattern is generated directly by ;; aarch64_expand_vec_perm_const, so any changes to the pattern would ;; need corresponding changes there. -(define_insn "aarch64_" +(define_insn "aarch64_" [(set (match_operand:VALL_F16 0 "register_operand" "=w") (unspec:VALL_F16 [(match_operand:VALL_F16 1 "register_operand" "w") (match_operand:VALL_F16 2 "register_operand" "w")] PERMUTE))] "TARGET_SIMD" - "\\t%0., %1., %2." + "\\t%0., %1., %2." [(set_attr "type" "neon_permute")] ) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index baba7318f20..c6ab217c8fd 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3356,13 +3356,13 @@ ;; Permutes that take half the elements from one vector and half the ;; elements from the other. -(define_insn "aarch64_sve_" +(define_insn "aarch64_sve_" [(set (match_operand:SVE_ALL 0 "register_operand" "=w") (unspec:SVE_ALL [(match_operand:SVE_ALL 1 "register_operand" "w") (match_operand:SVE_ALL 2 "register_operand" "w")] PERMUTE))] "TARGET_SVE" - "\t%0., %1., %2." + "\t%0., %1., %2." ) ;; Concatenate two vectors and extract a subvector. Note that the @@ -3395,13 +3395,13 @@ ;; Permutes that take half the elements from one vector and half the ;; elements from the other. -(define_insn "*aarch64_sve_" +(define_insn "*aarch64_sve_" [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") (unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa") (match_operand:PRED_ALL 2 "register_operand" "Upa")] PERMUTE))] "TARGET_SVE" - "\t%0., %1., %2." + "\t%0., %1., %2." ) ;; ========================================================================= diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 5b72dc4147b..f59052baf21 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1888,18 +1888,15 @@ (UNSPEC_AUTIA1716 "12") (UNSPEC_AUTIB1716 "14")]) -(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip") - (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn") - (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")]) +(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip1") (UNSPEC_ZIP2 "zip2") + (UNSPEC_TRN1 "trn1") (UNSPEC_TRN2 "trn2") + (UNSPEC_UZP1 "uzp1") (UNSPEC_UZP2 "uzp2")]) ; op code for REV instructions (size within which elements are reversed). (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32") (UNSPEC_REV16 "16")]) -(define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2") - (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2") - (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2") - (UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") +(define_int_attr perm_hilo [(UNSPEC_UNPACKSHI "hi") (UNSPEC_UNPACKUHI "hi") (UNSPEC_UNPACKSLO "lo") (UNSPEC_UNPACKULO "lo")]) ;; Return true if the associated optab refers to the high-numbered lanes,