From: lkcl <lkcl@web>
Date: Tue, 3 Sep 2019 16:10:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4169
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e401dbc73a349c251adfbc5c3f3eedccea00383;p=libreriscv.git

---

diff --git a/simple_v_extension/vblock_format/discussion.mdwn b/simple_v_extension/vblock_format/discussion.mdwn
index 257799fcf..aaf34e81b 100644
--- a/simple_v_extension/vblock_format/discussion.mdwn
+++ b/simple_v_extension/vblock_format/discussion.mdwn
@@ -35,9 +35,11 @@ When P64 Mode is enabled (0b10), the P64 prefix also follows:
 | ---------- | -     | ---------- |
 | P64-prefix | rsvd  | P48-Prefix |
 
-When Twin-SVP Mode is enabled (0b11), a *second* P48-P64 prefix pair follows
-in the VBLOCK, which applies vector-context from the *second* instruction's
-registers.
+When Twin-SVP Mode is enabled (0b11), a *second* P48 prefix follows after a P48-P64 pair,
+in the VBLOCK (another 16 bits after the 32 bit P48/P64 block), which applies vector-context from the *second* instruction's
+registers. The reason why Twin-SVP's prefix is only P48 is because P64 can change VL and MVL. It makes no srnse to try to reset VL/MVL twice in succession.
+
+VL/MVL from a P64 prefix is applied as if a [[SV.SETVL]] instruction had been executed as a hidden (first, implicit) instruction in the VBLOCK.
 
 # Rules