From: Michael Nolan <mtnolan2640@gmail.com>
Date: Thu, 28 May 2020 14:51:31 +0000 (-0400)
Subject: Fix test_isel to properly examine registers
X-Git-Tag: div_pipeline~766
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e47495275b43cc43e28f11da6fc36631bc107f2;p=soc.git

Fix test_isel to properly examine registers
---

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index 5a5c2035..afe7745c 100644
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -121,6 +121,8 @@ class CRTestCase(FHDLTestCase):
             initial_regs = [0] * 32
             initial_regs[2] = random.randint(0, (1<<64)-1)
             initial_regs[3] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst),
+                                 initial_regs=initial_regs, initial_cr=cr)
             self.run_tst_program(Program(lst), initial_cr=cr)
 
             
@@ -167,6 +169,17 @@ class TestRunner(FHDLTestCase):
             reg3 = simulator.gpr(reg3_sel).value
             yield alu.p.data_i.a.eq(reg3)
 
+        reg1_ok = yield dec2.e.read_reg1.ok
+        if reg1_ok:
+            reg1_sel = yield dec2.e.read_reg1.data
+            reg1 = simulator.gpr(reg1_sel).value
+            yield alu.p.data_i.a.eq(reg1)
+        reg2_ok = yield dec2.e.read_reg2.ok
+        if reg2_ok:
+            reg2_sel = yield dec2.e.read_reg2.data
+            reg2 = simulator.gpr(reg2_sel).value
+            yield alu.p.data_i.b.eq(reg2)
+
     def assert_outputs(self, alu, dec2, simulator, code):
         whole_reg = yield dec2.e.write_cr_whole
         cr_en = yield dec2.e.write_cr.ok