From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Mar 2020 12:39:28 +0000 (+0000)
Subject: comment out addr_we_i, seems not to be used
X-Git-Tag: div_pipeline~1695
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e4885bae9da984272a94c6d8e2e337a2d0a2a16;p=soc.git

comment out addr_we_i, seems not to be used
---

diff --git a/src/soc/scoreboard/addr_match.py b/src/soc/scoreboard/addr_match.py
index 3f48008a..895701ca 100644
--- a/src/soc/scoreboard/addr_match.py
+++ b/src/soc/scoreboard/addr_match.py
@@ -47,7 +47,7 @@ class PartialAddrMatch(Elaboratable):
         self.bitwid = bitwid
         # inputs
         self.addrs_i = Array(Signal(bitwid, name="addr") for i in range(n_adr))
-        self.addr_we_i = Signal(n_adr, reset_less=True) # write-enable
+        #self.addr_we_i = Signal(n_adr, reset_less=True) # write-enable
         self.addr_en_i = Signal(n_adr, reset_less=True) # address latched in
         self.addr_rs_i = Signal(n_adr, reset_less=True) # address deactivated
 
@@ -98,7 +98,7 @@ class PartialAddrMatch(Elaboratable):
 
     def __iter__(self):
         yield from self.addrs_i
-        yield self.addr_we_i
+        #yield self.addr_we_i
         yield self.addr_en_i
         yield from self.addr_nomatch_a_o
         yield self.addr_nomatch_o
@@ -228,7 +228,7 @@ class PartialAddrBitmap(PartialAddrMatch):
     def __iter__(self):
         yield from self.faddrs_i
         yield from self.len_i
-        yield self.addr_we_i
+        #yield self.addr_we_i
         yield self.addr_en_i
         yield from self.addr_nomatch_a_o
         yield self.addr_nomatch_o
diff --git a/src/soc/scoreboard/memfu.py b/src/soc/scoreboard/memfu.py
index 2989c8e0..553ebb5e 100644
--- a/src/soc/scoreboard/memfu.py
+++ b/src/soc/scoreboard/memfu.py
@@ -33,7 +33,7 @@ class MemFunctionUnits(Elaboratable):
         # address matching
         self.addrs_i = Array(Signal(self.bitwid, name="addrs_i%d" % i) \
                              for i in range(n_ldsts))
-        self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address
+        #self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address
         self.addr_en_i = Signal(n_ldsts) # address latched in
         self.addr_rs_i = Signal(n_ldsts) # address deactivated
 
@@ -93,7 +93,7 @@ class MemFunctionUnits(Elaboratable):
         # connect address matching: these get connected to the Addr CUs
         for i in range(self.n_ldsts):
             comb += intregdeps.addrs_i[i].eq(self.addrs_i[i])
-        comb += intregdeps.addr_we_i.eq(self.addr_we_i)
+        #comb += intregdeps.addr_we_i.eq(self.addr_we_i)
         comb += intregdeps.addr_en_i.eq(self.addr_en_i)
         comb += intregdeps.addr_rs_i.eq(self.addr_rs_i)
 
@@ -113,7 +113,7 @@ class MemFunctionUnits(Elaboratable):
         yield self.go_die_i
         yield self.fn_issue_i
         yield from self.addrs_i
-        yield self.addr_we_i
+        #yield self.addr_we_i
         yield self.addr_en_i
 
     def ports(self):