From: lkcl <lkcl@web>
Date: Mon, 14 Mar 2022 00:15:22 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3064
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e4c539be093a75f8affb8ed11f19ec19b0b2a30;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index a72b06114..f69773276 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -153,7 +153,6 @@ Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/v
 
 ## ternlogi
 
-
 | 0.5|6.10|11.15|16.20| 21..28|29.30|31|
 | -- | -- | --- | --- | ----- | --- |--|
 | NN | RT | RA  | RB  | im0-7 |  00 |Rc|
@@ -346,8 +345,15 @@ grevlut should be arranged so as to produce the constants
 needed to put into bext (bitextract) so as in turn to
 be able to emulate x86 pmovmask instructions <https://www.felixcloutier.com/x86/pmovmskb>.
 This only requires 2 instructions (grevlut, bext).
-The following
-settings provide the required mask constants:
+
+Note that if the mask is required to be placed
+directly into CR Fields (for use as CR Predicate
+masks rather than a integer mask) then sv.ori
+may be used instead:
+
+    sv.ori./elwid=8 r10.v, r10.v, 0
+
+The following settings provide the required mask constants:
 
 | RA       | RB      | imm        | iv | result        |
 | -------  | ------- | ---------- | -- | ----------    |