From: Florent Kermarrec Date: Tue, 23 Dec 2014 18:44:39 +0000 (+0100) Subject: add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system... X-Git-Tag: 24jan2021_ls180~2572^2~76 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e5a4ab097d16aa2f793053f2f1835e481725003;p=litex.git add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock --- diff --git a/lib/sata/bist.py b/lib/sata/bist.py index 2de4962f..1ee2f001 100644 --- a/lib/sata/bist.py +++ b/lib/sata/bist.py @@ -8,6 +8,8 @@ class SATABISTUnit(Module): source = sata_con.sink self.start = Signal() + self.write_only = Signal() + self.read_only = Signal() self.sector = Signal(48) self.count = Signal(4) self.done = Signal() @@ -31,7 +33,11 @@ class SATABISTUnit(Module): If(self.start, self.ctrl_error_counter.reset.eq(1), self.data_error_counter.reset.eq(1), - NextState("SEND_WRITE_CMD_AND_DATA") + If(self.read_only, + NextState("SEND_READ_CMD") + ).Else( + NextState("SEND_WRITE_CMD_AND_DATA") + ) ) ) fsm.act("SEND_WRITE_CMD_AND_DATA", @@ -53,7 +59,11 @@ class SATABISTUnit(Module): If(~sink.write | ~sink.success | sink.failed, self.ctrl_error_counter.ce.eq(1) ), - NextState("SEND_READ_CMD") + If(self.write_only, + NextState("IDLE") + ).Else( + NextState("SEND_READ_CMD") + ) ) ) fsm.act("SEND_READ_CMD", @@ -94,6 +104,9 @@ class SATABIST(Module, AutoCSR): self._start = CSR() self._start_sector = CSRStorage(48) self._count = CSRStorage(4) + self._write_only = CSRStorage() + self._read_only = CSRStorage() + self._stop = CSRStorage() self._sector = CSRStatus(48) @@ -104,8 +117,10 @@ class SATABIST(Module, AutoCSR): count = self._count.storage stop = self._stop.storage - update = Signal() + compute = Signal() + write_only = self._write_only.storage + read_only = self._read_only.storage sector = self._sector.status errors = self._errors.status @@ -113,6 +128,8 @@ class SATABIST(Module, AutoCSR): self.unit = SATABISTUnit(sata_con) self.comb += [ + self.unit.write_only.eq(write_only), + self.unit.read_only.eq(read_only), self.unit.sector.eq(sector), self.unit.count.eq(count) ] @@ -131,13 +148,13 @@ class SATABIST(Module, AutoCSR): ) fsm.act("WAIT_DONE", If(self.unit.done, - NextState("CHECK_PREPARE") + NextState("COMPUTE") ).Elif(stop, NextState("IDLE") ) ) - fsm.act("CHECK_PREPARE", - update.eq(1), + fsm.act("COMPUTE", + compute.eq(1), NextState("START") ) @@ -145,7 +162,7 @@ class SATABIST(Module, AutoCSR): If(start, errors.eq(0), sector.eq(start_sector) - ).Elif(update, + ).Elif(compute, errors.eq(errors + self.unit.data_errors), sector.eq(sector + count) ) diff --git a/targets/test.py b/targets/test.py index e1f79ea1..f16b3e5a 100644 --- a/targets/test.py +++ b/targets/test.py @@ -40,7 +40,7 @@ class _CRG(Module): i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, # 100MHz - p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, + p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=, @@ -111,7 +111,7 @@ class SimDesign(UART2WB): default_platform = "kc705" def __init__(self, platform, export_mila=False): - clk_freq = 200*1000000 + clk_freq = 100*1000000 UART2WB.__init__(self, platform, clk_freq) self.crg = _CRG(platform) @@ -162,7 +162,7 @@ class TestDesign(UART2WB, AutoCSR): csr_map.update(UART2WB.csr_map) def __init__(self, platform, export_mila=False): - clk_freq = 200*1000000 + clk_freq = 100*1000000 UART2WB.__init__(self, platform, clk_freq) self.crg = _CRG(platform) diff --git a/test/bist.py b/test/bist.py new file mode 100644 index 00000000..00b38109 --- /dev/null +++ b/test/bist.py @@ -0,0 +1,77 @@ +import time +import argparse +from config import * + +sector_size = 512 + +class SATABISTDriver: + def __init__(self, regs): + self.regs = regs + self.last_sector = 0 + self.last_time = time.time() + self.last_errors = 0 + self.mode = "rw" + + def set_mode(self, mode): + self.mode = mode + self.regs.bist_write_only.write(0) + self.regs.bist_read_only.write(0) + if mode == "wr": + self.regs.bist_write_only.write(1) + if mode == "rd": + self.regs.bist_read_only.write(1) + + def start(self, sector, count, mode): + self.set_mode(mode) + self.regs.bist_start_sector.write(sector) + self.regs.bist_count.write(count) + self.regs.bist_stop.write(0) + self.regs.bist_start.write(1) + + def stop(self): + self.regs.bist_stop.write(1) + + def show_status(self): + errors = self.regs.bist_errors.read() - self.last_errors + self.last_errors += errors + + sector = self.regs.bist_sector.read() + n = sector - self.last_sector + self.last_sector = sector + + t = self.last_time - time.time() + self.last_time = time.time() + + if self.mode in ["wr", "rd"]: + speed_mult = 1 + else: + speed_mult = 2 + print("%4.2f MB/sec errors=%d sector=%d" %(n*sector_size*speed_mult/(1024*1024), errors, sector)) + + +def _get_args(): + parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter, + description="""\ +SATA BIST utility. +""") + parser.add_argument("-s", "--sector", default=0, help="BIST start sector") + parser.add_argument("-c", "--count", default=4, help="BIST count (number of sectors per transaction)") + parser.add_argument("-m", "--mode", default="rw", help="BIST mode (rw, wr, rd") + + return parser.parse_args() + +if __name__ == "__main__": + args = _get_args() + wb.open() + ### + bist = SATABISTDriver(wb.regs) + try: + bist.start(int(args.sector), int(args.count), args.mode) + while True: + bist.show_status() + time.sleep(1) + except KeyboardInterrupt: + pass + bist.stop() + ### + wb.close() diff --git a/test/test_bist.py b/test/test_bist.py deleted file mode 100644 index 3d80bcb1..00000000 --- a/test/test_bist.py +++ /dev/null @@ -1,48 +0,0 @@ -import time -from config import * -from tools import * - -sector_size = 512 - -wb.open() -### -class SATABISTDriver: - def __init__(self, regs): - self.regs = regs - self.last_sector = 0 - self.last_time = time.time() - self.last_errors = 0 - - def start_loopback(self, sector, count): - self.regs.bist_start_sector.write(sector) - self.regs.bist_count.write(count) - self.regs.bist_stop.write(0) - self.regs.bist_start.write(1) - - def stop(self): - self.regs.bist_stop.write(1) - - def show_status(self): - errors = self.regs.bist_errors.read() - self.last_errors - self.last_errors += errors - - sector = self.regs.bist_sector.read() - n = sector - self.last_sector - self.last_sector = sector - - t = self.last_time - time.time() - self.last_time = time.time() - - print("%4.2f Mb/sec errors=%d sector=%d" %(n*512*8*2/(1024*1024), errors, sector)) - -bist = SATABISTDriver(wb.regs) -try: - bist.start_loopback(0, 4) - while True: - bist.show_status() - time.sleep(1) -except KeyboardInterrupt: - pass -bist.stop() -### -wb.close()