From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sat, 23 May 2020 13:07:12 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e5fa4fb32193d2b50506761e2e70f43dcce4a02;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
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diff --git a/85/e195982a71772c909b7275559302683f7bcf08 b/85/e195982a71772c909b7275559302683f7bcf08
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+Date: Sat, 23 May 2020 13:07:12 +0000
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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