From: David S. Miller Date: Mon, 5 Sep 2011 16:00:53 +0000 (+0000) Subject: sparc-opts.h (PROCESSOR_NIAGARA3, [...]): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e64c239dd9a97ce13c6c69d42247d0187854f09;p=gcc.git sparc-opts.h (PROCESSOR_NIAGARA3, [...]): New. * config/sparc/sparc-opts.h (PROCESSOR_NIAGARA3, PROCESSOR_NIAGARA4): New. * config/sparc/sparc.opt: Handle new processor types. * config/sparc/sparc.md: Add to "cpu" attribute. * config/sparc/sparc.h (TARGET_CPU_niagara3, TARGET_CPU_niagara4): New, treat as niagara2. * config/sparc/linux64.h: Handle niagara3 and niagara4 like niagara2. * config/sparc/sol2.h: Likewise. * config/sparc/niagara2.md: Schedule niagara3 like niagara2. * config/sparc/sparc.c (sparc_option_override): Add niagara3 and niagara4 handling. (sparc32_initialize_trampoline): Likewise. (sparc64_initialize_trampoline): Likewise. (sparc_use_sched_lookahead): Likewise. (sparc_issue_rate): Likewise. (sparc_register_move_cost): Likewise. * config/sparc/driver-sparc.c (cpu_names): Use niagara3 and niagara4 as appropriate. * doc/invoke.texi: Document new processor types. From-SVN: r178554 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e605ce2f518..569994d8c21 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -8,6 +8,28 @@ * doc/invoke.texi: Document that Linux also supports -mcpu=native and -mtune=native on sparc. + * config/sparc/sparc-opts.h (PROCESSOR_NIAGARA3, + PROCESSOR_NIAGARA4): New. + * config/sparc/sparc.opt: Handle new processor types. + * config/sparc/sparc.md: Add to "cpu" attribute. + * config/sparc/sparc.h (TARGET_CPU_niagara3, + TARGET_CPU_niagara4): New, treat as niagara2. + * config/sparc/linux64.h: Handle niagara3 and niagara4 + like niagara2. + * config/sparc/sol2.h: Likewise. + * config/sparc/niagara2.md: Schedule niagara3 like + niagara2. + * config/sparc/sparc.c (sparc_option_override): Add + niagara3 and niagara4 handling. + (sparc32_initialize_trampoline): Likewise. + (sparc64_initialize_trampoline): Likewise. + (sparc_use_sched_lookahead): Likewise. + (sparc_issue_rate): Likewise. + (sparc_register_move_cost): Likewise. + * config/sparc/driver-sparc.c (cpu_names): Use niagara3 + and niagara4 as appropriate. + * doc/invoke.texi: Document new processor types. + 2011-09-05 Georg-Johann Lay PR target/50289 diff --git a/gcc/config/sparc/driver-sparc.c b/gcc/config/sparc/driver-sparc.c index f6a4e7c9922..96227289db5 100644 --- a/gcc/config/sparc/driver-sparc.c +++ b/gcc/config/sparc/driver-sparc.c @@ -55,8 +55,8 @@ static const struct cpu_names { { "UltraSPARC-T2", "niagara2" }, { "UltraSPARC-T2", "niagara2" }, { "UltraSPARC-T2+", "niagara2" }, - { "SPARC-T3", "niagara2" }, - { "SPARC-T4", "niagara2" }, + { "SPARC-T3", "niagara3" }, + { "SPARC-T4", "niagara4" }, #else { "SuperSPARC", "supersparc" }, { "HyperSparc", "hypersparc" }, @@ -71,8 +71,8 @@ static const struct cpu_names { { "Serrano", "ultrasparc3" }, { "UltraSparc T1", "niagara" }, { "UltraSparc T2", "niagara2" }, - { "UltraSparc T3", "niagara2" }, - { "UltraSparc T4", "niagara2" }, + { "UltraSparc T3", "niagara3" }, + { "UltraSparc T4", "niagara4" }, #endif { NULL, NULL } }; diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h index 0ad1a5234a1..c4997bb29b4 100644 --- a/gcc/config/sparc/linux64.h +++ b/gcc/config/sparc/linux64.h @@ -35,7 +35,9 @@ along with GCC; see the file COPYING3. If not see || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ - || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 /* A 64 bit v9 compiler with stack-bias, in a Medium/Low code model environment. */ diff --git a/gcc/config/sparc/niagara2.md b/gcc/config/sparc/niagara2.md index 298ebe013f9..9d899f288d9 100644 --- a/gcc/config/sparc/niagara2.md +++ b/gcc/config/sparc/niagara2.md @@ -1,5 +1,5 @@ -;; Scheduling description for Niagara-2. -;; Copyright (C) 2007 Free Software Foundation, Inc. +;; Scheduling description for Niagara-2 and Niagara-3. +;; Copyright (C) 2007, 2011 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -17,74 +17,74 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -;; Niagara-2 is a single-issue processor. +;; Niagara-2 and Niagara-3 are single-issue processors. (define_automaton "niagara2_0") (define_cpu_unit "niag2_pipe" "niagara2_0") (define_insn_reservation "niag2_25cycle" 25 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "flushw")) "niag2_pipe*25") (define_insn_reservation "niag2_5cycle" 5 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "multi,flushw,iflush,trap")) "niag2_pipe*5") (define_insn_reservation "niag2_6cycle" 4 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "savew")) "niag2_pipe*4") /* Most basic operations are single-cycle. */ (define_insn_reservation "niag2_ialu" 1 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "ialu,shift,compare,cmove")) "niag2_pipe") (define_insn_reservation "niag2_imul" 5 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "imul")) "niag2_pipe*5") (define_insn_reservation "niag2_idiv" 31 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "idiv")) "niag2_pipe*31") (define_insn_reservation "niag2_branch" 5 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) "niag2_pipe*5") (define_insn_reservation "niag2_3cycle_load" 3 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "load,fpload")) "niag2_pipe*3") (define_insn_reservation "niag2_1cycle_store" 1 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "store,fpstore")) "niag2_pipe") (define_insn_reservation "niag2_fp" 3 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "fpmove,fpcmove,fpcrmove,fpcmp,fpmul")) "niag2_pipe*3") (define_insn_reservation "niag2_fdivs" 19 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "fpdivs")) "niag2_pipe*19") (define_insn_reservation "niag2_fdivd" 33 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "fpdivd")) "niag2_pipe*33") (define_insn_reservation "niag2_vis" 6 - (and (eq_attr "cpu" "niagara2") + (and (eq_attr "cpu" "niagara2,niagara3") (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist")) "niag2_pipe*6") diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h index 86afbbefe52..bd58c9f8c7b 100644 --- a/gcc/config/sparc/sol2.h +++ b/gcc/config/sparc/sol2.h @@ -121,6 +121,28 @@ along with GCC; see the file COPYING3. If not see #define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 +#undef CPP_CPU64_DEFAULT_SPEC +#define CPP_CPU64_DEFAULT_SPEC "" +#undef ASM_CPU32_DEFAULT_SPEC +#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb" +#undef ASM_CPU64_DEFAULT_SPEC +#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b" +#undef ASM_CPU_DEFAULT_SPEC +#define ASM_CPU_DEFAULT_SPEC ASM_CPU32_DEFAULT_SPEC +#endif + /* Both Sun as and GNU as understand -K PIC. */ #undef ASM_SPEC #define ASM_SPEC ASM_SPEC_BASE ASM_PIC_SPEC @@ -131,7 +153,7 @@ along with GCC; see the file COPYING3. If not see %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \ %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{!mcpu*:%(cpp_cpu_default)} \ " @@ -218,7 +240,9 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); %{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ %{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ %{mcpu=niagara2:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ -%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}}} \ +%{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ +%{mcpu=niagara4:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \ +%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}}}}} \ %{!mcpu*:%(asm_cpu_default)} \ " diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index aef69b4d3c9..266cb1403ac 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -42,6 +42,8 @@ enum processor_type { PROCESSOR_ULTRASPARC3, PROCESSOR_NIAGARA, PROCESSOR_NIAGARA2, + PROCESSOR_NIAGARA3, + PROCESSOR_NIAGARA4, PROCESSOR_NATIVE }; diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index de9a7eb6929..cf9e1971562 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -709,6 +709,8 @@ sparc_option_override (void) { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 }, { TARGET_CPU_niagara, PROCESSOR_NIAGARA }, { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 }, + { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 }, + { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 }, { -1, PROCESSOR_V7 } }; const struct cpu_default *def; @@ -749,6 +751,10 @@ sparc_option_override (void) MASK_V9|MASK_DEPRECATED_V8_INSNS}, /* UltraSPARC T2 */ { MASK_ISA, MASK_V9}, + /* UltraSPARC T3 */ + { MASK_ISA, MASK_V9}, + /* UltraSPARC T4 */ + { MASK_ISA, MASK_V9}, }; const struct cpu_table *cpu; unsigned int i; @@ -857,7 +863,9 @@ sparc_option_override (void) && (sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA - || sparc_cpu == PROCESSOR_NIAGARA2)) + || sparc_cpu == PROCESSOR_NIAGARA2 + || sparc_cpu == PROCESSOR_NIAGARA3 + || sparc_cpu == PROCESSOR_NIAGARA4)) align_functions = 32; /* Validate PCC_STRUCT_RETURN. */ @@ -909,6 +917,8 @@ sparc_option_override (void) sparc_costs = &niagara_costs; break; case PROCESSOR_NIAGARA2: + case PROCESSOR_NIAGARA3: + case PROCESSOR_NIAGARA4: sparc_costs = &niagara2_costs; break; case PROCESSOR_NATIVE: @@ -923,7 +933,9 @@ sparc_option_override (void) maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, ((sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_NIAGARA - || sparc_cpu == PROCESSOR_NIAGARA2) + || sparc_cpu == PROCESSOR_NIAGARA2 + || sparc_cpu == PROCESSOR_NIAGARA3 + || sparc_cpu == PROCESSOR_NIAGARA4) ? 2 : (sparc_cpu == PROCESSOR_ULTRASPARC3 ? 8 : 3)), @@ -933,7 +945,9 @@ sparc_option_override (void) ((sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA - || sparc_cpu == PROCESSOR_NIAGARA2) + || sparc_cpu == PROCESSOR_NIAGARA2 + || sparc_cpu == PROCESSOR_NIAGARA3 + || sparc_cpu == PROCESSOR_NIAGARA4) ? 64 : 32), global_options.x_param_values, global_options_set.x_param_values); @@ -8342,7 +8356,9 @@ sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) if (sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA - && sparc_cpu != PROCESSOR_NIAGARA2) + && sparc_cpu != PROCESSOR_NIAGARA2 + && sparc_cpu != PROCESSOR_NIAGARA3 + && sparc_cpu != PROCESSOR_NIAGARA4) emit_insn (gen_flush (validize_mem (adjust_address (m_tramp, SImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure @@ -8385,7 +8401,9 @@ sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) if (sparc_cpu != PROCESSOR_ULTRASPARC && sparc_cpu != PROCESSOR_ULTRASPARC3 && sparc_cpu != PROCESSOR_NIAGARA - && sparc_cpu != PROCESSOR_NIAGARA2) + && sparc_cpu != PROCESSOR_NIAGARA2 + && sparc_cpu != PROCESSOR_NIAGARA3 + && sparc_cpu != PROCESSOR_NIAGARA4) emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); /* Call __enable_execute_stack after writing onto the stack to make sure @@ -8578,7 +8596,9 @@ static int sparc_use_sched_lookahead (void) { if (sparc_cpu == PROCESSOR_NIAGARA - || sparc_cpu == PROCESSOR_NIAGARA2) + || sparc_cpu == PROCESSOR_NIAGARA2 + || sparc_cpu == PROCESSOR_NIAGARA3 + || sparc_cpu == PROCESSOR_NIAGARA4) return 0; if (sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3) @@ -8597,6 +8617,8 @@ sparc_issue_rate (void) { case PROCESSOR_NIAGARA: case PROCESSOR_NIAGARA2: + case PROCESSOR_NIAGARA3: + case PROCESSOR_NIAGARA4: default: return 1; case PROCESSOR_V9: @@ -9635,7 +9657,9 @@ sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, if (sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 || sparc_cpu == PROCESSOR_NIAGARA - || sparc_cpu == PROCESSOR_NIAGARA2) + || sparc_cpu == PROCESSOR_NIAGARA2 + || sparc_cpu == PROCESSOR_NIAGARA3 + || sparc_cpu == PROCESSOR_NIAGARA4) return 12; return 6; diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index 81308e79b3d..afdca1e3aab 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -208,8 +208,8 @@ extern enum cmodel sparc_cmodel; which requires the following macro to be true if enabled. Prior to V9, there are no instructions to even talk about memory synchronization. Note that the UltraSPARC III processors don't implement RMO, unlike the - UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO - either. + UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not + implement RMO either. Default to false; for example, Solaris never enables RMO, only ever uses total memory ordering (TMO). */ @@ -247,12 +247,16 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_ultrasparc3 10 #define TARGET_CPU_niagara 11 #define TARGET_CPU_niagara2 12 +#define TARGET_CPU_niagara3 13 +#define TARGET_CPU_niagara4 14 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ - || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 #define CPP_CPU32_DEFAULT_SPEC "" #define ASM_CPU32_DEFAULT_SPEC "" @@ -281,6 +285,14 @@ extern enum cmodel sparc_cmodel; #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" #define ASM_CPU64_DEFAULT_SPEC "-Av9b" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC "-Av9b" +#endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC "-Av9b" +#endif #else @@ -373,6 +385,8 @@ extern enum cmodel sparc_cmodel; %{mcpu=ultrasparc3:-D__sparc_v9__} \ %{mcpu=niagara:-D__sparc_v9__} \ %{mcpu=niagara2:-D__sparc_v9__} \ +%{mcpu=niagara3:-D__sparc_v9__} \ +%{mcpu=niagara4:-D__sparc_v9__} \ %{!mcpu*:%(cpp_cpu_default)} \ " #define CPP_ARCH32_SPEC "" @@ -417,6 +431,8 @@ extern enum cmodel sparc_cmodel; %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ %{mcpu=niagara:%{!mv8plus:-Av9b}} \ %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ +%{mcpu=niagara3:%{!mv8plus:-Av9b}} \ +%{mcpu=niagara4:%{!mv8plus:-Av9b}} \ %{!mcpu*:%(asm_cpu_default)} \ " @@ -1658,8 +1674,8 @@ do { \ On Niagara, normal branches insert 3 bubbles into the pipe and annulled branches insert 4 bubbles. - On Niagara-2, a not-taken branch costs 1 cycle whereas a taken - branch costs 6 cycles. */ + On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas + a taken branch costs 6 cycles. */ #define BRANCH_COST(speed_p, predictable_p) \ ((sparc_cpu == PROCESSOR_V9 \ @@ -1669,7 +1685,8 @@ do { \ ? 9 \ : (sparc_cpu == PROCESSOR_NIAGARA \ ? 4 \ - : (sparc_cpu == PROCESSOR_NIAGARA2 \ + : ((sparc_cpu == PROCESSOR_NIAGARA2 \ + || sparc_cpu == PROCESSOR_NIAGARA3) \ ? 5 \ : 3)))) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 7d5d6dc4410..721db934a36 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -115,7 +115,9 @@ ultrasparc, ultrasparc3, niagara, - niagara2" + niagara2, + niagara3, + niagara4" (const (symbol_ref "sparc_cpu_attr"))) ;; Attribute for the instruction set. diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 84bf2883c4b..ce6fa94fde8 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -154,6 +154,12 @@ Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA) EnumValue Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2) +EnumValue +Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3) + +EnumValue +Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4) + mcmodel= Target RejectNegative Joined Var(sparc_cmodel_string) Use given SPARC-V9 code model diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 66d9fc5e29b..c5b19ebaf5c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17283,7 +17283,8 @@ for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, -@samp{ultrasparc3}, @samp{niagara} and @samp{niagara2}. +@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, +and @samp{niagara4}. Native Solaris and Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -17302,7 +17303,7 @@ implementations. v8: supersparc, hypersparc, leon sparclite: f930, f934, sparclite86x sparclet: tsc701 - v9: ultrasparc, ultrasparc3, niagara, niagara2 + v9: ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 @end smallexample By default (unless configured otherwise), GCC generates code for the V7 @@ -17341,7 +17342,10 @@ optimizes it for the Sun UltraSPARC I/II/IIi chips. With Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With @option{-mcpu=niagara}, the compiler additionally optimizes it for Sun UltraSPARC T1 chips. With @option{-mcpu=niagara2}, the compiler -additionally optimizes it for Sun UltraSPARC T2 chips. +additionally optimizes it for Sun UltraSPARC T2 chips. With +@option{-mcpu=niagara3}, the compiler additionally optimizes it for Sun +UltraSPARC T3 chips. With @option{-mcpu=niagara4}, the compiler +additionally optimizes it for Sun UltraSPARC T4 chips. @item -mtune=@var{cpu_type} @opindex mtune @@ -17354,8 +17358,8 @@ The same values for @option{-mcpu=@var{cpu_type}} can be used for that select a particular CPU implementation. Those are @samp{cypress}, @samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3}, -@samp{niagara}, and @samp{niagara2}. With native Solaris and Linux -toolchains, @samp{native} can also be used. +@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. With +native Solaris and Linux toolchains, @samp{native} can also be used. @item -mv8plus @itemx -mno-v8plus