From: Kenneth Graunke <kenneth@whitecape.org>
Date: Thu, 1 Nov 2018 23:11:31 +0000 (-0700)
Subject: iris: Disable a PIPE_CONTROL workaround on Icelake
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e6aaa1ba5c706046daa4c0e45551a17c867a9b3;p=mesa.git

iris: Disable a PIPE_CONTROL workaround on Icelake
---

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 12741c7a899..86975e279e1 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -4776,7 +4776,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, uint32_t flags,
     * We do these now because they may add post-sync operations or CS stalls.
     */
 
-   if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
+   if (GEN_GEN < 11 && flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) {
       /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate
        *
        * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or