From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 12 Jun 2018 08:54:20 +0000 (+0200)
Subject: soc/cores/cpu: add add_sources static method
X-Git-Tag: 24jan2021_ls180~1703
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e723d152a34a2f550a47a4f280b4da67e7596be;p=litex.git

soc/cores/cpu: add add_sources static method

When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
---

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 03d99efc..2ab62c78 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -56,6 +56,10 @@ class LM32(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index f607d044..8ce397db 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -105,6 +105,10 @@ class MOR1KX(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)),
             "verilog", "rtl", "verilog")
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index dbce1c64..ace7ee93 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -118,6 +118,10 @@ class PicoRV32(Module):
         ]
 
         # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, "picorv32.v"))
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 68aea9dd..d9434742 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -44,7 +44,11 @@ class VexRiscv(Module):
                                   i_dBusWishbone_ACK=d.ack,
                                   i_dBusWishbone_ERR=d.err)
 
-        # add Verilog sources
+        # add verilog sources
+        self.add_sources(platform)
+
+    @staticmethod
+    def add_sources(platform):
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir), "VexRiscv.v")
         platform.add_verilog_include_path(vdir)