From: Cole Poirier Date: Thu, 30 Jul 2020 18:02:43 +0000 (-0700) Subject: Update 3d_gpu/180nm_single_core_test_asic_memlayout_F1 to F2, Data[0:15] X-Git-Tag: convert-csv-opcode-to-binary~2307 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e724a7fa1e690bf2990dcd5b1f75cda8aceba84;p=libreriscv.git Update 3d_gpu/180nm_single_core_test_asic_memlayout_F1 to F2, Data[0:15] is now Data[0:127] --- diff --git a/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg b/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg deleted file mode 100644 index b756c3a73..000000000 --- a/3d_gpu/180nm_single_core_test_asic_memlayout_F1.svg +++ /dev/null @@ -1,3902 +0,0 @@ - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - Wishbone D/64 - - - - - - - - - - - - - - - - - RGB/TTL - QSPI - DRAM - SDMMC - NO L2 - - - - FU0 - FU1 - FU3 - FU4 - FU5 - FU6 - FU2 - FU7 - Addr[12:48] - Addr[4]=0 - Bytemask[0:15] - A[5:11] - Data[0:15] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Addr[4]=1 - Bytemask[0:15] - A[5:11] - Data[0:15] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Addr[12:48] - Single Entry - - - Addr[5:11] - Double Entry - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - L1 Odd - (Addr[4]=1) - - Wishbone D/64 - - - - - - - D/128 - D/64 - - - - - - - - - - - - - D/128 - DataMerger2 - - - - PriorityPicker - - - - - - - 128 to 64 - bit Arbiters - - - - - - - - - - - - Select FU0-FU7 >= N - Merge Bytemask > N - - DataMerger - - - - - - - - - L1 Even - (Addr[4]=0) - - Wishbone D/64 - D/128 - D/128 - D/64 - - - - - - - - - - - - - DataMerger1 - - - - - - - - Addr[5:] - Bytemask - Data - Addr[4]? - - - - - - - - - - - - - - - - - - - - - - - - - - Addr - Len - Data - - LDSTCU1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU6 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - Addr - Len - Data - - LDSTCU7 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PortInterface(Even) - PortInterface(Odd) - LDSTSplitter - PortInterface - - - - - - - - - - - - - - - - - - - LDSTCU0 - Addr - Len - Data - - - - - PortInterface - - - Addr[5:] - Bytemask - Data - - diff --git a/3d_gpu/180nm_single_core_test_asic_memlayout_F2.svg b/3d_gpu/180nm_single_core_test_asic_memlayout_F2.svg new file mode 100644 index 000000000..be4f659ef --- /dev/null +++ b/3d_gpu/180nm_single_core_test_asic_memlayout_F2.svg @@ -0,0 +1,3902 @@ + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + Wishbone D/64 + + + + + + + + + + + + + + + + + RGB/TTL + QSPI + DRAM + SDMMC + NO L2 + + + + FU0 + FU1 + FU3 + FU4 + FU5 + FU6 + FU2 + FU7 + Addr[12:48] + Addr[4]=0 + Bytemask[0:15] + A[5:11] + Data[0:127] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Addr[4]=1 + Bytemask[0:15] + A[5:11] + Data[0:127] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Addr[12:48] + Single Entry + + + Addr[5:11] + Double Entry + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + L1 Odd + (Addr[4]=1) + + Wishbone D/64 + + + + + + + D/128 + D/64 + + + + + + + + + + + + + D/128 + DataMerger2 + + + + PriorityPicker + + + + + + + 128 to 64 + bit Arbiters + + + + + + + + + + + + Select FU0-FU7 >= N + Merge Bytemask > N + + DataMerger + + + + + + + + + L1 Even + (Addr[4]=0) + + Wishbone D/64 + D/128 + D/128 + D/64 + + + + + + + + + + + + + DataMerger1 + + + + + + + + Addr[5:] + Bytemask + Data + Addr[4]? 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