From: Mateusz Holenko <mholenko@antmicro.com>
Date: Tue, 23 Jul 2019 09:48:00 +0000 (+0200)
Subject: cpu/vexriscv: bump submodule
X-Git-Tag: 24jan2021_ls180~1082^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e89c56468a5f6e46f894180d1f0a5242f944f10;p=litex.git

cpu/vexriscv: bump submodule
---

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 03f7f9d4..747a2e01 160000
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 03f7f9d46c9c862e1ef3ebbe19b5113b882e4358
+Subproject commit 747a2e012f43d13c3487acc3c758477aad277559