From: Mike Frysinger Date: Fri, 5 Jun 2015 13:17:19 +0000 (+0800) Subject: allow interactive "reg" command to dump all registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e8ad1eab377710dd1f2df192bdec20536b11840;p=riscv-isa-sim.git allow interactive "reg" command to dump all registers It you want to scan all the registers at once (or at least a few), having to dump them one by one is kind of a pain. Change the behavior so that if the register number is omitted, it'll dump all of them. --- diff --git a/riscv/interactive.cc b/riscv/interactive.cc index 689b53a..6ae1892 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -109,7 +109,7 @@ void sim_t::interactive_help(const std::string& cmd, const std::vector # Display in \n" + "reg [reg] # Display [reg] (all if omitted) in \n" "fregs # Display single precision in \n" "fregd # Display double precision in \n" "pc # Show current PC in \n" @@ -213,7 +213,17 @@ reg_t sim_t::get_freg(const std::vector& args) void sim_t::interactive_reg(const std::string& cmd, const std::vector& args) { - fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args)); + if (args.size() == 1) { + // Show all the regs! + processor_t *p = get_core(args[0]); + + for (int r = 0; r < NFPR; ++r) { + fprintf(stderr, "%-4s: 0x%016" PRIx64 " ", xpr_name[r], p->state.XPR[r]); + if ((r + 1) % 4 == 0) + fprintf(stderr, "\n"); + } + } else + fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args)); } union fpr