From: Kristian H. Kristensen <hoegsberg@chromium.org>
Date: Fri, 21 Sep 2018 19:24:47 +0000 (-0700)
Subject: freedreno/a6xx: Build up draw dword0 outside visibilty if statement
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e905052248a6e9c0e1ce6b7f32ad5aeff28a7c8;p=mesa.git

freedreno/a6xx: Build up draw dword0 outside visibilty if statement

Pulling this logic out means we can share the logic and avoid a couple
of temporary variables that helped make things clearer before. Note
that in either vismode case, we always program vismode 0.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
---

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index 0b9ff43ead1..ba8b52810d5 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -81,26 +81,26 @@ draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
 		  const struct pipe_draw_info *info,
 		  unsigned index_offset)
 {
-	enum pc_di_src_sel src_sel;
-
 	if (info->index_size) {
 		assert(!info->has_user_indices);
 
 		struct pipe_resource *idx_buffer = info->index.resource;
 		uint32_t idx_size = info->index_size * info->count;
 		uint32_t idx_offset = index_offset + info->start * info->index_size;
-		enum a4xx_index_size idx_type = fd4_size2indextype(info->index_size);
-		src_sel = DI_SRC_SEL_DMA;
+
+		/* leave vis mode blank for now, it will be patched up when
+		 * we know if we are binning or not
+		 */
+		uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
+			CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
+			CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size)) |
+			0x2000;
 
 		OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
 		if (vismode == USE_VISIBILITY) {
-			/* leave vis mode blank for now, it will be patched up when
-			 * we know if we are binning or not
-			 */
-			OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0) | 0x2000,
-					  &batch->draw_patches);
+			OUT_RINGP(ring, draw, &batch->draw_patches);
 		} else {
-			OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode) | 0x2000);
+			OUT_RING(ring, draw);
 		}
 		OUT_RING(ring, info->instance_count);    /* NumInstances */
 		OUT_RING(ring, info->count);             /* NumIndices */
@@ -108,17 +108,18 @@ draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
 		OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
 		OUT_RING (ring, idx_size);
 	} else {
-		src_sel = DI_SRC_SEL_AUTO_INDEX;
+		/* leave vis mode blank for now, it will be patched up when
+		 * we know if we are binning or not
+		 */
+		uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
+			CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
+			0x2000;
 
 		OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
 		if (vismode == USE_VISIBILITY) {
-			/* leave vis mode blank for now, it will be patched up when
-			 * we know if we are binning or not
-			 */
-			OUT_RINGP(ring, DRAW4(primtype, src_sel, INDEX4_SIZE_32_BIT, 0) | 0x2000,
-					  &batch->draw_patches);
+			OUT_RINGP(ring, draw, &batch->draw_patches);
 		} else {
-			OUT_RING(ring, DRAW4(primtype, src_sel, INDEX4_SIZE_32_BIT, vismode) | 0x2000);
+			OUT_RING(ring, draw);
 		}
 		OUT_RING(ring, info->instance_count);    /* NumInstances */
 		OUT_RING(ring, info->count);             /* NumIndices */