From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 7 Jun 2017 21:17:58 +0000 (-0700)
Subject: Forbid S-mode execution from user memory
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3e92055f8323729fdfa72e4ac463ed677424606c;p=riscv-isa-sim.git

Forbid S-mode execution from user memory

https://github.com/riscv/riscv-isa-manual/commit/285c81746fe664060b62ae0584865dbfa9f42e1a
---

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 76a6ab1..54b5b1d 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -163,7 +163,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
   if (vm.levels == 0)
     return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen
 
-  bool supervisor = mode == PRV_S;
+  bool s_mode = mode == PRV_S;
   bool sum = get_field(proc->state.mstatus, MSTATUS_SUM);
   bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);
 
@@ -189,7 +189,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
 
     if (PTE_TABLE(pte)) { // next level of page table
       base = ppn << PGSHIFT;
-    } else if ((pte & PTE_U) ? supervisor && !sum : !supervisor) {
+    } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) {
       break;
     } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
       break;