From: lkcl <lkcl@web>
Date: Thu, 16 Jun 2022 19:07:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1750
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ea80070f6d696384ab627f145d331582e486844;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index b01d2964e..d1bcc4e73 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -249,7 +249,32 @@ easy to identify by looking for the EXT001 pattern. Once identified
 the 32/64 bits may be passed independently to multiple Decoders in
 parallel.
 
-# Single Predication
+# Predication.
+
+Predication is entirely missing from the Power ISA.
+Adding it would be a costly mistake because it cannot be retrofitted
+to an ISA without literally duplicating all instructions. Prefixing
+is about the only sane way to go.
+
+CR Fields as predicate masks could be spread across multiple register
+file entries, making them costly to read in one hit. Therefore the
+possibility exists that an instruction element writing to a CR Field
+could *overwrite* the Predicate mask CR Vector during the middle of
+a for-loop.
+
+Clearly this is bad, so don't do it.  If there are potential issues
+they can be avoided by using the crweird instructions to get CR Field
+bits into an Integer GPR (r3, r10 or r30) and use that GPR as a
+Predicate mask instead.
+
+Also, in Vertical-First Mode, usually used for looping in combination
+with svstep, predicates of both types (GPR, CR Field) should never be
+written to. The Predicate masks should be set, then Vertical-First mode
+set, and within the loop all Predicates used should be considered
+loop-invariant.  Given that Vertical-First is a type of Scalar execution
+mode, branches can and should be used on Scalar tests anyway.
+
+## Single Predication
 
 So named because there is a Twin Predication concept as well, Single
 Predication is also unlike other Vector ISAs because it allows zeroing
@@ -283,7 +308,7 @@ element indices getting "out-of-sync" even though the Predicate Mask
 is the same because the behaviour is different when zeros in the
 Predicate are encountered.
 
-# Twin Predication
+## Twin Predication
 
 Twin Predication is an entirely new concept not present in any commercial
 Vector ISA of the past forty years.  To explain how normal Single-predication