From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Wed, 6 Jun 2018 21:48:00 +0000 (+0530)
Subject: arch-power: Add fixed-point store conditional instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3eb1446b98e6a0aaf38d9460f97deed0575c463b;p=gem5.git

arch-power: Add fixed-point store conditional instructions

This adds the following store instructions:
  * Store Byte Conditional Indexed (stbcx.)
  * Store Halfword Conditional Indexed (sthcx.)
  * Store Doubleword Conditional Indexed (stdcx.)

Change-Id: I065113e817e2ae419a6f3231e645bacd95460607
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index f6cf30b50..0a5b839f0 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -292,7 +292,39 @@ decode PO default Unknown::unknown() {
 
         format StoreIndexOp {
             215: stbx({{ Mem_ub = Rs_ub; }});
+            694: stbcx({{
+                bool store_performed = false;
+                Mem_ub = Rs_ub;
+                if (Rsv) {
+                    if (RsvLen == 1) {
+                        if (RsvAddr == EA) {
+                            store_performed = true;
+                        }
+                    }
+                }
+                Xer xer = XER;
+                Cr cr = CR;
+                cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+                CR = cr;
+                Rsv = 0;
+            }});
             407: sthx({{ Mem_uh = Rs_uh; }});
+            726: sthcx({{
+                bool store_performed = false;
+                Mem_uh = Rs_uh;
+                if (Rsv) {
+                    if (RsvLen == 2) {
+                        if (RsvAddr == EA) {
+                            store_performed = true;
+                        }
+                    }
+                }
+                Xer xer = XER;
+                Cr cr = CR;
+                cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+                CR = cr;
+                Rsv = 0;
+            }});
             918: sthbrx({{ Mem_uh = swap_byte(Rs_uh); }});
             151: stwx({{ Mem_uw = Rs_uw; }});
             150: stwcx({{
@@ -313,6 +345,22 @@ decode PO default Unknown::unknown() {
             }});
             662: stwbrx({{ Mem_uw = swap_byte(Rs_uw); }});
             149: stdx({{ Mem = Rs }});
+            214: stdcx({{
+                bool store_performed = false;
+                Mem = Rs;
+                if (Rsv) {
+                    if (RsvLen == 8) {
+                        if (RsvAddr == EA) {
+                            store_performed = true;
+                        }
+                    }
+                }
+                Xer xer = XER;
+                Cr cr = CR;
+                cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
+                CR = cr;
+                Rsv = 0;
+            }});
             660: stdbrx({{ Mem = swap_byte(Rs); }});
         }