From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 04:20:08 +0000 (+0100)
Subject: whoops need to read RS in CR inputs test
X-Git-Tag: div_pipeline~699
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ebe0588c568cb56b3b7b29ff817622b0e01708a;p=soc.git

whoops need to read RS in CR inputs test
---

diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py
index b230be13..b1b6332d 100644
--- a/src/soc/fu/compunits/test/test_cr_compunit.py
+++ b/src/soc/fu/compunits/test/test_cr_compunit.py
@@ -41,11 +41,15 @@ class CRTestRunner(TestRunner):
                 cr3_sel = yield dec2.e.read_cr3.data
                 res['cr_c'] = sim.crl[cr3_sel].get_range().value
 
-        # RA
+        # RA/RC
         reg1_ok = yield dec2.e.read_reg1.ok
+        reg3_ok = yield dec2.e.read_reg3.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
             res['a'] = sim.gpr(data1).value
+        if reg3_ok:
+            data1 = yield dec2.e.read_reg3.data
+            res['a'] = sim.gpr(data1).value
 
         # RB (or immediate)
         reg2_ok = yield dec2.e.read_reg2.ok
@@ -53,13 +57,14 @@ class CRTestRunner(TestRunner):
             data2 = yield dec2.e.read_reg2.data
             res['b'] = sim.gpr(data2).value
 
+        print ("get inputs", res)
         return res
 
     def check_cu_outputs(self, res, dec2, sim, code):
         """naming (res) must conform to CRFunctionUnit output regspec
         """
 
-        print ("check extra output", repr(code))
+        print ("check extra output", repr(code), res)
 
         # full CR
         whole_reg = yield dec2.e.write_cr_whole
@@ -67,6 +72,7 @@ class CRTestRunner(TestRunner):
         if whole_reg:
             full_cr = res['full_cr']
             expected_cr = sim.cr.get_range().value
+            print(f"expected cr {expected_cr:x}, actual: {full_cr:x}")
             self.assertEqual(expected_cr, full_cr, code)
 
         # part-CR
diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 9879955c..c22a3b1e 100644
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -51,8 +51,8 @@ class CROutputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
         self.o = Data(64, name="o") # RA
-        self.full_cr = Data(32, name="cr_out") # CR in
-        self.cr = Data(4, name="cr_o")
+        self.full_cr = Data(32, name="full_cr")
+        self.cr = Data(4, name="cr")
 
     def __iter__(self):
         yield from super().__iter__()