From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Jun 2022 13:53:06 +0000 (+0100)
Subject: remove unnecessary ref
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ec62ed28d3784524cd8b0d28fd875251e4281a7;p=libreriscv.git

remove unnecessary ref
---

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 91da580f3..f9fd1eca6 100644
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -161,7 +161,7 @@ Main design principles
           Vectorisation "context" rather than adding new opcodes.
 	\item Does not modify or deviate from the underlying scalar
           Power ISA unless there's a significant performance boost or other
-          advantage in the vector space (see \ref{subsubsec:add_to_pow_isa})
+          advantage in the vector space
 	\item Aimed at Supercomputing: avoids creating significant
 	      \textit{sequential dependency hazards}, allowing \textbf{high
 	      performance multi-issue superscalar microarchitectures} to be