From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 23 Jun 2021 15:33:32 +0000 (+0100)
Subject: add VL and srcstep to ISACaller namespace
X-Git-Tag: xlen-bcd~409
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3eccec7c6a475b728bf8a370c53d9c942fc1999a;p=openpower-isa.git

add VL and srcstep to ISACaller namespace
---

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index dfbd0d1f..b8ec70b7 100644
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -82,7 +82,7 @@ def SHL64(value, bits, wordlen=64):
         bits = bits.value
     mask = (1 << wordlen) - 1
     bits = bits & (wordlen - 1)
-    return (value << bits) & mask
+    return SelectableInt((value << bits) & mask, 64)
 
 
 def ROTL64(value, bits):
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index e3ecbed6..141b6889 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -705,6 +705,12 @@ class ISACaller:
         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 
+        # add some SVSTATE convenience variables
+        vl = self.svstate.vl.asint(msb0=True)
+        srcstep = self.svstate.srcstep.asint(msb0=True)
+        self.namespace['VL'] = vl
+        self.namespace['srcstep'] = srcstep
+
     def handle_carry_(self, inputs, outputs, already_done):
         inv_a = yield self.dec2.e.do.invert_in
         if inv_a:
@@ -1392,6 +1398,7 @@ class ISACaller:
         self.namespace['NIA'] = self.pc.NIA
         self.namespace['SVSTATE'] = self.svstate.spr
 
+
 def inject():
     """Decorator factory.