From: lkcl Date: Tue, 18 Feb 2020 00:51:08 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~3356 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ecfd3e34a92ee41bf169a121631ecec67a2435e;p=libreriscv.git --- diff --git a/3d_gpu/tutorial.mdwn b/3d_gpu/tutorial.mdwn index c96e2066e..06f5d1a69 100644 --- a/3d_gpu/tutorial.mdwn +++ b/3d_gpu/tutorial.mdwn @@ -70,6 +70,8 @@ what is actually synthesised at the gate level. in nmigen, pay particular attention to "comb" (combinatorial) and "sync" (synchronous). comb is a sequence of gates without any clock-synchronised latches. with comb it is absolutely essential that you **do not** create a "loop" by mistake. i.e. combinatorial output must never, under any circumstances, loop back to combinatorial input. "comb" blocks must be DAGs (Directed Acyclic Graphs) in other words. "sync" will *automatically* create a clock synchronised register for you. this is how you construct pipelines. Also, if you want to create cyclic graphs, you absolutely **must** store partial results of combinatorial blocks in registers (with sync) *before* passing those partial results back into more (or the same) combinatorial blocks. +* http://www.clifford.at/yosys/cmd_proc.html + # verilog Verilog is really worth mentioning in passing. You will see it a lot. Verilog was designed in the 1980s, when the state of the art in computer programming was BASIC, FORTRAN, and, if you were lucky, PASCAL.