From: whitequark <whitequark@whitequark.org>
Date: Sat, 19 Jan 2019 01:37:58 +0000 (+0000)
Subject: lib.fifo: fix simulation read/write methods to take only one cycle.
X-Git-Tag: working~65
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ed51938;p=nmigen.git

lib.fifo: fix simulation read/write methods to take only one cycle.
---

diff --git a/nmigen/lib/fifo.py b/nmigen/lib/fifo.py
index d52c144..9bf927f 100644
--- a/nmigen/lib/fifo.py
+++ b/nmigen/lib/fifo.py
@@ -63,11 +63,10 @@ class FIFOInterface:
     def read(self):
         """Read method for simulation."""
         assert (yield self.readable)
-        value = (yield self.dout)
         yield self.re.eq(1)
         yield
+        value = (yield self.dout)
         yield self.re.eq(0)
-        yield
         return value
 
     def write(self, data):
@@ -77,7 +76,6 @@ class FIFOInterface:
         yield self.we.eq(1)
         yield
         yield self.we.eq(0)
-        yield
 
 
 def _incr(signal, modulo):