From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 15 Mar 2022 05:11:13 +0000 (-0700)
Subject: rename bitmanip_inlines -> bitmanip
X-Git-Tag: opf_rfc_ls005_v1~3058
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3edabea4aaacbc6f1ecfddc0bed1259fac180076;p=libreriscv.git

rename bitmanip_inlines -> bitmanip
---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index d5a059dbb..1f8a21b6c 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -632,7 +632,7 @@ temp = clmul((RA), (RB)) ^ (RC)
 `cldivrem` isn't an actual instruction, but is just used in the pseudo-code
 for other instructions.
 
-[[!inline pagenames="openpower/sv/bitmanip_inlines/cldivrem.py" raw="true" feeds="no" actions="yes"]]
+[[!inline pagenames="openpower/sv/bitmanip/cldivrem.py" raw="true" feeds="no" actions="yes"]]
 
 ## `cldiv` Carry-less Division
 
diff --git a/openpower/sv/bitmanip/cldivrem.py b/openpower/sv/bitmanip/cldivrem.py
new file mode 100644
index 000000000..5bf49b120
--- /dev/null
+++ b/openpower/sv/bitmanip/cldivrem.py
@@ -0,0 +1,34 @@
+def cldivrem(n, d, width):
+    """ Carry-less Division and Remainder.
+        `n` and `d` are integers, `width` is the number of bits needed to hold
+        each input/output.
+        Returns a tuple `q, r` of the quotient and remainder.
+    """
+    assert d != 0, "TODO: decide what happens on division by zero"
+    assert 0 <= n < 1 << width, f"bad n (doesn't fit in {width}-bit uint)"
+    assert 0 <= d < 1 << width, f"bad d (doesn't fit in {width}-bit uint)"
+    r = n
+    q = 0
+    r_shift = 0
+    d_shift = 0
+    msb = 1 << (width - 1)
+    for _ in range(width):
+        if r & msb:
+            if d & msb:
+                r ^= d
+                q |= 1
+            else:
+                d <<= 1
+                d_shift += 1
+        else:
+            if d & msb:
+                r <<= 1
+                q <<= 1
+                r_shift += 1
+            else:
+                r <<= 1
+                r_shift += 1
+                d <<= 1
+                d_shift += 1
+    r >>= r_shift
+    return q, r
diff --git a/openpower/sv/bitmanip_inlines/cldivrem.py b/openpower/sv/bitmanip_inlines/cldivrem.py
deleted file mode 100644
index 5bf49b120..000000000
--- a/openpower/sv/bitmanip_inlines/cldivrem.py
+++ /dev/null
@@ -1,34 +0,0 @@
-def cldivrem(n, d, width):
-    """ Carry-less Division and Remainder.
-        `n` and `d` are integers, `width` is the number of bits needed to hold
-        each input/output.
-        Returns a tuple `q, r` of the quotient and remainder.
-    """
-    assert d != 0, "TODO: decide what happens on division by zero"
-    assert 0 <= n < 1 << width, f"bad n (doesn't fit in {width}-bit uint)"
-    assert 0 <= d < 1 << width, f"bad d (doesn't fit in {width}-bit uint)"
-    r = n
-    q = 0
-    r_shift = 0
-    d_shift = 0
-    msb = 1 << (width - 1)
-    for _ in range(width):
-        if r & msb:
-            if d & msb:
-                r ^= d
-                q |= 1
-            else:
-                d <<= 1
-                d_shift += 1
-        else:
-            if d & msb:
-                r <<= 1
-                q <<= 1
-                r_shift += 1
-            else:
-                r <<= 1
-                r_shift += 1
-                d <<= 1
-                d_shift += 1
-    r >>= r_shift
-    return q, r