From: Nick Clifton Date: Wed, 15 Jun 2016 15:25:34 +0000 (+0100) Subject: Fix simple gas testsuite failures. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ee6e4fbec4a4e0451f20efce50acb720e921a9f;p=binutils-gdb.git Fix simple gas testsuite failures. binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 reloc. gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the instruction size. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mn10200.c (md_assemble): Likewise. * config/tc-moxie.c (md_assemble): Likewise. * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of exception targets. Add alpha, hppa, microblaze and rl78 to list of exceptions. (forward): Add microblaze to list of exceptions. (fwdexp): Add alpha to list of exceptions. (redef2): Add arm-epoc-pe and rl78 to list of exceptions. (redef3): Add rl78 and x86_64 cygwin to list of exceptions. (do_930509a): Alpha sort list of exception targets. Add h8300 and mn10200 to list of exceptions. (align2): Expect to fail for nds32. (cond): Add alpha and rl78 to list of exceptions. * testsuite/gas/all/none.d: Skip for ft32 and hppa. * testsuite/gas/all/string.d: Skip for tic4x. * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff target does not support ELF. * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH tests for sh-pe and sh-rtemscoff targets. * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to list of exceptions. (type): Run the noifunc version for alpha-freebsd and visium. * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, mn10200 or moxie targets. * testsuite/gas/ft32/insn.d: Update expected disassembly. * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin targets. * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for mcore and rx targets. * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, rl78 and vax. (purge): Expect to fail on the ns32k and vax. * testsuite/gas/nds32/alu-2.d: Update expected disassembly. * testsuite/gas/nds32/ls.d: Likewise. * testsuite/gas/nds32/sys-reg.d: Likewise. * testsuite/gas/nds32/usr-spe-reg.d: Likewise. * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. * testsuite/gas/pe/section-align-3.d: Likewise. * testsuite/gas/pe/section-exclude.d: Likewise. * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required data has been seen. * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow for variations in whitespace. * testsuite/gas/tilepro/t_constants.d: Pass once all the required data has been seen. * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. Installs a 32-bit value without generating warnings on 64-bit hosts. Use the new macro to replace the .word directives. opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer constants to match expected behaviour. (nds32_parse_opcode): Likewise. Also for whitespace. --- diff --git a/binutils/ChangeLog b/binutils/ChangeLog index e8e80b364f6..5f52ed96789 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2016-06-15 Nick Clifton + + * readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 + reloc. + 2016-06-14 John Baldwin * objcopy.c (do_elf_stt_common): Use correct type. diff --git a/binutils/readelf.c b/binutils/readelf.c index 25ccb6a7dde..ac278a4da38 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -11833,6 +11833,8 @@ is_24bit_abs_reloc (unsigned int reloc_type) case EM_CYGNUS_MN10200: case EM_MN10200: return reloc_type == 4; /* R_MN10200_24. */ + case EM_FT32: + return reloc_type == 5; /* R_FT32_20. */ default: return FALSE; } diff --git a/gas/ChangeLog b/gas/ChangeLog index eba7ddf8c14..64b62af1d84 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,61 @@ +2016-06-15 Nick Clifton + + * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the + instruction size. + * config/tc-mcore.c (md_assemble): Likewise. + * config/tc-mn10200.c (md_assemble): Likewise. + * config/tc-moxie.c (md_assemble): Likewise. + * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. + * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of + exception targets. Add alpha, hppa, microblaze and rl78 to list + of exceptions. + (forward): Add microblaze to list of exceptions. + (fwdexp): Add alpha to list of exceptions. + (redef2): Add arm-epoc-pe and rl78 to list of exceptions. + (redef3): Add rl78 and x86_64 cygwin to list of exceptions. + (do_930509a): Alpha sort list of exception targets. Add h8300 and + mn10200 to list of exceptions. + (align2): Expect to fail for nds32. + (cond): Add alpha and rl78 to list of exceptions. + * testsuite/gas/all/none.d: Skip for ft32 and hppa. + * testsuite/gas/all/string.d: Skip for tic4x. + * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff + target does not support ELF. + * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. + * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. + * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH + tests for sh-pe and sh-rtemscoff targets. + * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to + list of exceptions. + (type): Run the noifunc version for alpha-freebsd and visium. + * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, + mn10200 or moxie targets. + * testsuite/gas/ft32/insn.d: Update expected disassembly. + * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin + targets. + * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for + mcore and rx targets. + * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, + rl78 and vax. + (purge): Expect to fail on the ns32k and vax. + * testsuite/gas/nds32/alu-2.d: Update expected disassembly. + * testsuite/gas/nds32/ls.d: Likewise. + * testsuite/gas/nds32/sys-reg.d: Likewise. + * testsuite/gas/nds32/usr-spe-reg.d: Likewise. + * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. + * testsuite/gas/pe/section-align-3.d: Likewise. + * testsuite/gas/pe/section-exclude.d: Likewise. + * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required + data has been seen. + * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow + for variations in whitespace. + * testsuite/gas/tilepro/t_constants.d: Pass once all the required + data has been seen. + * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. + Installs a 32-bit value without generating warnings on 64-bit + hosts. + Use the new macro to replace the .word directives. + 2016-06-15 Andrew Burgess * testsuite/gas/arc/add_s.d: New file. diff --git a/gas/config/tc-ft32.c b/gas/config/tc-ft32.c index 505d12667fa..37642bd20f6 100644 --- a/gas/config/tc-ft32.c +++ b/gas/config/tc-ft32.c @@ -393,6 +393,8 @@ md_assemble (char *str) output[idx++] = 0xff & (b >> 16); output[idx++] = 0xff & (b >> 24); + dwarf2_emit_insn (4); + while (ISSPACE (*op_end)) op_end++; diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c index f8b934dca63..9c80388e429 100644 --- a/gas/config/tc-mcore.c +++ b/gas/config/tc-mcore.c @@ -1598,6 +1598,9 @@ md_assemble (char * str) output[0] = INST_BYTE0 (inst); output[1] = INST_BYTE1 (inst); +#ifdef OBJ_ELF + dwarf2_emit_insn (2); +#endif check_literals (opcode->transfer, isize); } diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c index 1831b9fd1c5..8275c1ae16e 100644 --- a/gas/config/tc-mn10200.c +++ b/gas/config/tc-mn10200.c @@ -1154,7 +1154,7 @@ keep_going: abort (); /* Write out the instruction. */ - dwarf2_emit_insn (0); + dwarf2_emit_insn (size); if (relaxable && fc > 0) { /* On a 64-bit host the size of an 'int' is not the same diff --git a/gas/config/tc-moxie.c b/gas/config/tc-moxie.c index 9201cb58262..7e6a8cf446a 100644 --- a/gas/config/tc-moxie.c +++ b/gas/config/tc-moxie.c @@ -540,6 +540,7 @@ md_assemble (char *str) } md_number_to_chars (p, iword, 2); + dwarf2_emit_insn (2); while (ISSPACE (*op_end)) op_end++; diff --git a/gas/config/tc-pj.c b/gas/config/tc-pj.c index 37fd4814977..e4a0379f5b6 100644 --- a/gas/config/tc-pj.c +++ b/gas/config/tc-pj.c @@ -440,6 +440,10 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg ATTRIBUTE_UNUSED) } break; + case BFD_RELOC_PJ_CODE_REL32: + fixP->fx_done = 0; + return; + default: abort (); } diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 5c71c1cb7bd..d5d2445ab63 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -50,19 +50,21 @@ if { ![istarget cris-*-*] && ![istarget crisv32-*-*] # This test is meaningless for the PA; the difference of two undefined # symbols is something that is (and must be) supported on the PA. -# The same is true for alpha-vms +# The same is true for ALPHA-VMS. # -# The MN10300 port supports link time relaxation which in turn allows -# for link time resolution of the differneces of two symbols which are -# undefined at assembly time. Hence this test will not pass for the -# MN10300. The same thing is true for the RX and AVR port as well. -if { ![istarget hppa*-*-*] - && ![istarget alpha*-*-*vms*] +# The AVR, MICROBLAZE, MN10300, RL78 and RX ports all support link time +# relaxation, which in turn allows for link time resolution of the +# differences of two previously undefined symbols. Hence this test will +# not pass for these targets. +if { ![istarget alpha*-*-*vms*] + && ![istarget am3*-*-*] && ![istarget avr-*-*] - && ![istarget rx-*-*] + && ![istarget hppa*-*-*] + && ![istarget microblaze-*-*] && ![istarget mn10300-*-*] && ![istarget msp430*-*-*] - && ![istarget am3*-*-*] } then { + && ![istarget rl78-*-*] + && ![istarget rx-*-*] } then { gas_test_error "diff1.s" "" "difference of two undefined symbols" } @@ -96,6 +98,7 @@ case $target_triplet in { { h8300*-*-* } { } { hppa*-*-* } { } { mep-*-* } { } + { microblaze-*-* } { } { mn10\[23\]00*-*-* } { } default { # Some targets don't manage to resolve BFD_RELOC_8 for constants. @@ -115,6 +118,8 @@ if { ![is_aout_format] } { { hppa*64*-*-* } { run_dump_test fwdexp } + { alpha-*-*linux*ecoff } { } + { alpha-*-osf* } { } { hppa*-*-hpux* } { } { mep-*-* } { } { mmix-*-* } { } @@ -150,12 +155,13 @@ case $target_triplet in { { z80-*-* } { } default { run_dump_test redef + setup_xfail "arm-epoc-pe*" # These targets fail redef2 because they disallow redefined # symbols on relocs. - setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" + setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" run_dump_test redef2 - setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" + setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*" setup_xfail "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*" # rs6000-aix disallows redefinition via .comm. setup_xfail "*-*-aix*" @@ -167,7 +173,8 @@ case $target_triplet in { # failures. setup_xfail "bfin-*-*" "i\[3-7\]86-*-*coff" \ "i\[3-7\]86-*-*pe" "i\[3-7\]86-*-go32*" \ - "i\[3-7\]86-*-cygwin*" "i\[3-7\]86-*-mingw*" "x86_64-*-mingw*" + "i\[3-7\]86-*-cygwin*" "i\[3-7\]86-*-mingw*" \ + "x86_64-*-cygwin*" "x86_64-*-mingw*" run_dump_test redef3 gas_test_error "redef4.s" "" ".set for symbol already used as label" gas_test_error "redef5.s" "" ".set for symbol already defined through .comm" @@ -261,16 +268,17 @@ proc do_930509a {} { # C54x assembler (for compatibility) does not allow differences between # forward references. # C30 counts a four byte offset as a difference of one. -if { ![istarget hppa*-*-*] && - ![istarget cr16*-*-*] && - ![istarget crx*-*-*] && - ![istarget *c30*-*-*] && - ![istarget *c4x*-*-*] && - ![istarget *c54x*-*-*] } then { - # the vax fails because VMS can apparently actually handle this +if { ![istarget *c30*-*-*] + && ![istarget *c4x*-*-*] + && ![istarget *c54x*-*-*] + && ![istarget cr16*-*-*] + && ![istarget crx*-*-*] + && ![istarget h8300*-*-*] + && ![istarget hppa*-*-*] } then { + # The vax fails because VMS can apparently actually handle this # case in relocs, so gas doesn't handle it itself. - # msp430 and mn10300 emit two relocs to handle the difference of two symbols. - setup_xfail "mn10300*-*-*" "msp430*-*-*" "vax*-*-vms*" + # msp430 and mn10[23]00 emit two relocs to handle the difference of two symbols. + setup_xfail "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "vax*-*-vms*" do_930509a } @@ -283,6 +291,7 @@ case $target_triplet in { default { run_dump_test struct run_dump_test align + setup_xfail "ns32k-*-*" run_dump_test align2 } } @@ -349,11 +358,14 @@ proc test_cond {} { # This test is not suitable for the PA for various reasons # not limited to the fact that it depends on specific section # names appearing in the output file. -# again, p2align doesn't work on c54x target +# Again, p2align doesn't work on c54x and related targets. case $target_triplet in { + { alpha-*-linux*ecoff} { } + { alpha-*-osf*} { } { hppa*-*-* } { } { *c4x*-*-* } { } { *c54x*-*-* } { } + { rl78-*-* } { } { rx-*-* } { } default { test_cond diff --git a/gas/testsuite/gas/all/none.d b/gas/testsuite/gas/all/none.d index 82e495ba050..2b2f1cbb298 100644 --- a/gas/testsuite/gas/all/none.d +++ b/gas/testsuite/gas/all/none.d @@ -1,4 +1,6 @@ #objdump: -r -w +# The HPPA maps R_PARISC_PCREL64 onto BFD_RELOC_NONE. +#skip: ft32-*-* hppa*-*-* #... 0+ .*(NONE|NULL|UNUSED0) +\*ABS\* diff --git a/gas/testsuite/gas/all/string.d b/gas/testsuite/gas/all/string.d index b8bfd846cc1..5408ab03ff5 100644 --- a/gas/testsuite/gas/all/string.d +++ b/gas/testsuite/gas/all/string.d @@ -1,5 +1,6 @@ #objdump : -s -j .data -j "\$DATA\$" #name : .strings tests +#skip: tic4x-* .*: .* diff --git a/gas/testsuite/gas/alpha/alpha.exp b/gas/testsuite/gas/alpha/alpha.exp index 212566418c2..7cd5f15c3f6 100644 --- a/gas/testsuite/gas/alpha/alpha.exp +++ b/gas/testsuite/gas/alpha/alpha.exp @@ -20,11 +20,14 @@ if { [istarget alpha*-*-*] } then { - set elf [expr [istarget *-*-elf*] \ + set elf [expr [istarget *-*-elf*] \ || [istarget *-*-linux*] \ || [istarget *-*-freebsd*] \ || [istarget *-*-kfreebsd*-gnu] \ || [istarget *-*-netbsd*] ] + if { [istarget *-*-linux*ecoff] } then { + set elf 0 + } if $elf { run_dump_test "elf-reloc-1" diff --git a/gas/testsuite/gas/arm/blx-bl-convert.d b/gas/testsuite/gas/arm/blx-bl-convert.d index 9c251631af7..8c568c236af 100644 --- a/gas/testsuite/gas/arm/blx-bl-convert.d +++ b/gas/testsuite/gas/arm/blx-bl-convert.d @@ -1,7 +1,7 @@ #name: blx->bl convert under no -march/cpu #error-output: blx-bl-convert.l #objdump: -d -#skip: *-*-pe *-wince-* *-*-coff *-*-vxworks *-*-netbsdelf +#skip: *-*-pe *-wince-* *-*-coff *-*-vxworks *-*-netbsdelf *-*-nto* .*: file format .* diff --git a/gas/testsuite/gas/cfi/cfi-alpha-2.d b/gas/testsuite/gas/cfi/cfi-alpha-2.d index 4a87da2d9a5..cd7c9dd1498 100644 --- a/gas/testsuite/gas/cfi/cfi-alpha-2.d +++ b/gas/testsuite/gas/cfi/cfi-alpha-2.d @@ -1,7 +1,7 @@ #objdump: -r -j .eh_frame #name: CFI on alpha, 2 -.*: file format elf64-alpha +.*: file format elf64-alpha.* RELOCATION RECORDS FOR \[\.eh_frame\]: OFFSET TYPE VALUE diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp index 4a8d3bae62a..9b6012e1031 100644 --- a/gas/testsuite/gas/cfi/cfi.exp +++ b/gas/testsuite/gas/cfi/cfi.exp @@ -64,6 +64,25 @@ if { [istarget "i*86-*-*"] || [istarget "x86_64-*-*"] } then { run_dump_test "cfi-alpha-2" run_dump_test "cfi-alpha-3" +} elseif { [istarget "arc*-*-*"] } then { + run_dump_test "cfi-arc-1" + +} elseif { [istarget "arm*-*"] } then { + # Only ELF based ARM targets support CFI. + if { [is_pecoff_format] } then { + return + } + run_dump_test "cfi-arm-1" + +} elseif { [istarget "hppa*-linux*"] } then { + run_dump_test "cfi-hppa-1" + +} elseif { [istarget "m68*-*"] && ![istarget "m68hc1*-*"] } then { + run_dump_test "cfi-m68k" + +} elseif { [istarget "mips*-*"] } then { + run_dump_test "cfi-mips-1" + } elseif { [istarget powerpc*-*-*] } then { run_dump_test "cfi-ppc-1" @@ -73,8 +92,15 @@ if { [istarget "i*86-*-*"] || [istarget "x86_64-*-*"] } then { run_dump_test "cfi-s390x-1" } -} elseif { [istarget "m68*-*"] && ![istarget "m68hc1*-*"] } then { - run_dump_test "cfi-m68k" +} elseif [istarget "sh*-*"] then { + if { [istarget "*-pe" ] || [istarget "*-rtemscoff*"] } then { + return + } + + if { [istarget sh64*-*-*] || [istarget sh5*-*-*] } then { + } else { + run_dump_test "cfi-sh-1" + } } elseif { [istarget sparc*-*-*] } then { global NM @@ -86,24 +112,6 @@ if { [istarget "i*86-*-*"] || [istarget "x86_64-*-*"] } then { run_dump_test "cfi-sparc64-1" } -} elseif [istarget "sh*-*"] then { - if { [istarget sh64*-*-*] || [istarget sh5*-*-*] } then { - } else { - run_dump_test "cfi-sh-1" - } -} elseif { [istarget "arc*-*-*"] } then { - run_dump_test "cfi-arc-1" -} elseif { [istarget "arm*-*"] } then { - # Only ELF based ARM targets support CFI. - if { [is_pecoff_format] } then { - return - } - run_dump_test "cfi-arm-1" - -} elseif { [istarget "mips*-*"] } then { - run_dump_test "cfi-mips-1" -} elseif { [istarget "hppa*-linux*"] } then { - run_dump_test "cfi-hppa-1" } else { return } diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index b5f8fec0bff..95c9204e469 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -133,6 +133,7 @@ if { [is_elf_format] } then { } case $target_triplet in { { alpha*-*-* } { } + { *c54x*-*-* } { } { cr16*-*-* } { } { crx*-*-* } { } { h8300-*-* } { } @@ -142,14 +143,14 @@ if { [is_elf_format] } then { { mn10200-*-* } { } { mn10300-*-* } { } { msp43*-*-* } { } - { *c54x*-*-* } { } + { rl78-*-* } { } { rx-*-* } { } default { # The next test can fail if the target does not convert fixups # against ordinary symbols into relocations against section symbols. # This is usually revealed by the error message: # symbol `sym' required but not present - setup_xfail "m681*-*-*" "m68hc*-*-*" + setup_xfail "m681*-*-*" "m68hc*-*-*" "xgate-*-*" "vax-*-*" run_dump_test redef run_dump_test equ-reloc } @@ -183,10 +184,13 @@ if { [is_elf_format] } then { # The non-eabi ARM ports sets it to ELFOSABI_ARM. # So for these targets we cannot include an IFUNC symbol type # in the symbol type test. - if { [istarget "*-*-hpux*"] - || [istarget "visium-*-*"] + # The Alpha FreeBSD target does not support unique objects. + if { [istarget "*-*-hpux*"] + || [istarget "alpha*-*-*freebsd*"] + || [istarget "arm*-*-*"] || [istarget "msp*-*-*"] - || [istarget "arm*-*-*"]} then { + || [istarget "visium-*-*"] + } then { # hppa64 has a non-standard common directive if { ![istarget "hppa64*-*-hpux*"] } then { run_elf_list_test "type-noifunc" "" "" "-s" "| grep \"1 *\\\[FONTC\\\]\"" diff --git a/gas/testsuite/gas/elf/warn-2.s b/gas/testsuite/gas/elf/warn-2.s index 9800cd4839e..5094fdc3d8a 100644 --- a/gas/testsuite/gas/elf/warn-2.s +++ b/gas/testsuite/gas/elf/warn-2.s @@ -20,4 +20,4 @@ .endif .endif -;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* v850*-*-* } 0 } +;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* v850*-*-* } 0 } diff --git a/gas/testsuite/gas/ft32/insn.d b/gas/testsuite/gas/ft32/insn.d index cdaa1405222..f9b643a5d69 100644 --- a/gas/testsuite/gas/ft32/insn.d +++ b/gas/testsuite/gas/ft32/insn.d @@ -13,7 +13,7 @@ Disassembly of section .text: 8: f0 01 00 44 440001f0 add.l \$r0,\$r0,\$r31 c: 40 00 11 44 44110040 add.l \$r1,\$r2,\$r4 10: 00 00 88 44 44880000 add.l \$r8,\$r16,\$r0 - 14: 00 60 f0 45 45f06000 add.l \$r31,\$r0,0 + 14: 00 60 f0 45 45f06000 add.l \$r31,\$r0,200 18: 00 c0 0f 44 440fc000 move.l \$r0,\$r31 1c: 10 c0 0f 44 440fc010 add.l \$r0,\$r31,1 20: f0 df 0f 44 440fdff0 add.l \$r0,\$r31,1ff @@ -26,8 +26,8 @@ Disassembly of section .text: 3c: f2 01 00 44 440001f2 sub.l \$r0,\$r0,\$r31 40: 42 00 11 44 44110042 sub.l \$r1,\$r2,\$r4 44: 02 00 88 44 44880002 sub.l \$r8,\$r16,\$r0 - 48: 02 60 f0 45 45f06002 sub.l \$r31,\$r0,0 - 4c: 02 c0 0f 44 440fc002 sub.l \$r0,\$r31,0 + 48: 02 60 f0 45 45f06002 sub.l \$r31,\$r0,200 + 4c: 02 c0 0f 44 440fc002 sub.l \$r0,\$r31,0 50: 12 c0 0f 44 440fc012 sub.l \$r0,\$r31,1 54: f2 df 0f 44 440fdff2 sub.l \$r0,\$r31,1ff 58: 12 80 0f 42 420f8012 sub.s \$r0,\$r31,\$r1 @@ -39,8 +39,8 @@ Disassembly of section .text: 70: f4 01 00 44 440001f4 and.l \$r0,\$r0,\$r31 74: 44 00 11 44 44110044 and.l \$r1,\$r2,\$r4 78: 04 00 88 44 44880004 and.l \$r8,\$r16,\$r0 - 7c: 04 60 f0 45 45f06004 and.l \$r31,\$r0,0 - 80: 04 c0 0f 44 440fc004 and.l \$r0,\$r31,0 + 7c: 04 60 f0 45 45f06004 and.l \$r31,\$r0,200 + 80: 04 c0 0f 44 440fc004 and.l \$r0,\$r31,0 84: 14 c0 0f 44 440fc014 and.l \$r0,\$r31,1 88: f4 df 0f 44 440fdff4 and.l \$r0,\$r31,1ff 8c: 14 80 0f 42 420f8014 and.s \$r0,\$r31,\$r1 @@ -52,8 +52,8 @@ Disassembly of section .text: a4: f5 01 00 44 440001f5 or.l \$r0,\$r0,\$r31 a8: 45 00 11 44 44110045 or.l \$r1,\$r2,\$r4 ac: 05 00 88 44 44880005 or.l \$r8,\$r16,\$r0 - b0: 05 60 f0 45 45f06005 or.l \$r31,\$r0,0 - b4: 05 c0 0f 44 440fc005 or.l \$r0,\$r31,0 + b0: 05 60 f0 45 45f06005 or.l \$r31,\$r0,200 + b4: 05 c0 0f 44 440fc005 or.l \$r0,\$r31,0 b8: 15 c0 0f 44 440fc015 or.l \$r0,\$r31,1 bc: f5 df 0f 44 440fdff5 or.l \$r0,\$r31,1ff c0: 15 80 0f 42 420f8015 or.s \$r0,\$r31,\$r1 @@ -65,8 +65,8 @@ Disassembly of section .text: d8: f6 01 00 44 440001f6 xor.l \$r0,\$r0,\$r31 dc: 46 00 11 44 44110046 xor.l \$r1,\$r2,\$r4 e0: 06 00 88 44 44880006 xor.l \$r8,\$r16,\$r0 - e4: 06 60 f0 45 45f06006 xor.l \$r31,\$r0,0 - e8: 06 c0 0f 44 440fc006 xor.l \$r0,\$r31,0 + e4: 06 60 f0 45 45f06006 xor.l \$r31,\$r0,200 + e8: 06 c0 0f 44 440fc006 xor.l \$r0,\$r31,0 ec: 16 c0 0f 44 440fc016 xor.l \$r0,\$r31,1 f0: f6 df 0f 44 440fdff6 xor.l \$r0,\$r31,1ff f4: 16 80 0f 42 420f8016 xor.s \$r0,\$r31,\$r1 @@ -78,8 +78,8 @@ Disassembly of section .text: 10c: f7 01 00 44 440001f7 xnor.l \$r0,\$r0,\$r31 110: 47 00 11 44 44110047 xnor.l \$r1,\$r2,\$r4 114: 07 00 88 44 44880007 xnor.l \$r8,\$r16,\$r0 - 118: 07 60 f0 45 45f06007 xnor.l \$r31,\$r0,0 - 11c: 07 c0 0f 44 440fc007 xnor.l \$r0,\$r31,0 + 118: 07 60 f0 45 45f06007 xnor.l \$r31,\$r0,200 + 11c: 07 c0 0f 44 440fc007 xnor.l \$r0,\$r31,0 120: 17 c0 0f 44 440fc017 xnor.l \$r0,\$r31,1 124: f7 df 0f 44 440fdff7 xnor.l \$r0,\$r31,1ff 128: 17 80 0f 42 420f8017 xnor.s \$r0,\$r31,\$r1 @@ -91,8 +91,8 @@ Disassembly of section .text: 140: f8 01 00 44 440001f8 ashl.l \$r0,\$r0,\$r31 144: 48 00 11 44 44110048 ashl.l \$r1,\$r2,\$r4 148: 08 00 88 44 44880008 ashl.l \$r8,\$r16,\$r0 - 14c: 08 60 f0 45 45f06008 ashl.l \$r31,\$r0,0 - 150: 08 c0 0f 44 440fc008 ashl.l \$r0,\$r31,0 + 14c: 08 60 f0 45 45f06008 ashl.l \$r31,\$r0,200 + 150: 08 c0 0f 44 440fc008 ashl.l \$r0,\$r31,0 154: 18 c0 0f 44 440fc018 ashl.l \$r0,\$r31,1 158: f8 df 0f 44 440fdff8 ashl.l \$r0,\$r31,1ff 15c: 18 80 0f 42 420f8018 ashl.s \$r0,\$r31,\$r1 @@ -104,8 +104,8 @@ Disassembly of section .text: 174: f9 01 00 44 440001f9 lshr.l \$r0,\$r0,\$r31 178: 49 00 11 44 44110049 lshr.l \$r1,\$r2,\$r4 17c: 09 00 88 44 44880009 lshr.l \$r8,\$r16,\$r0 - 180: 09 60 f0 45 45f06009 lshr.l \$r31,\$r0,0 - 184: 09 c0 0f 44 440fc009 lshr.l \$r0,\$r31,0 + 180: 09 60 f0 45 45f06009 lshr.l \$r31,\$r0,200 + 184: 09 c0 0f 44 440fc009 lshr.l \$r0,\$r31,0 188: 19 c0 0f 44 440fc019 lshr.l \$r0,\$r31,1 18c: f9 df 0f 44 440fdff9 lshr.l \$r0,\$r31,1ff 190: 19 80 0f 42 420f8019 lshr.s \$r0,\$r31,\$r1 @@ -117,8 +117,8 @@ Disassembly of section .text: 1a8: fa 01 00 44 440001fa ashr.l \$r0,\$r0,\$r31 1ac: 4a 00 11 44 4411004a ashr.l \$r1,\$r2,\$r4 1b0: 0a 00 88 44 4488000a ashr.l \$r8,\$r16,\$r0 - 1b4: 0a 60 f0 45 45f0600a ashr.l \$r31,\$r0,0 - 1b8: 0a c0 0f 44 440fc00a ashr.l \$r0,\$r31,0 + 1b4: 0a 60 f0 45 45f0600a ashr.l \$r31,\$r0,200 + 1b8: 0a c0 0f 44 440fc00a ashr.l \$r0,\$r31,0 1bc: 1a c0 0f 44 440fc01a ashr.l \$r0,\$r31,1 1c0: fa df 0f 44 440fdffa ashr.l \$r0,\$r31,1ff 1c4: 1a 80 0f 42 420f801a ashr.s \$r0,\$r31,\$r1 @@ -130,8 +130,8 @@ Disassembly of section .text: 1dc: f1 01 00 44 440001f1 ror.l \$r0,\$r0,\$r31 1e0: 41 00 11 44 44110041 ror.l \$r1,\$r2,\$r4 1e4: 01 00 88 44 44880001 ror.l \$r8,\$r16,\$r0 - 1e8: 01 60 f0 45 45f06001 ror.l \$r31,\$r0,0 - 1ec: 01 c0 0f 44 440fc001 ror.l \$r0,\$r31,0 + 1e8: 01 60 f0 45 45f06001 ror.l \$r31,\$r0,200 + 1ec: 01 c0 0f 44 440fc001 ror.l \$r0,\$r31,0 1f0: 11 c0 0f 44 440fc011 ror.l \$r0,\$r31,1 1f4: f1 df 0f 44 440fdff1 ror.l \$r0,\$r31,1ff 1f8: 11 80 0f 42 420f8011 ror.s \$r0,\$r31,\$r1 @@ -143,8 +143,8 @@ Disassembly of section .text: 210: f3 01 00 44 440001f3 ldl.l \$r0,\$r0,\$r31 214: 43 00 11 44 44110043 ldl.l \$r1,\$r2,\$r4 218: 03 00 88 44 44880003 ldl.l \$r8,\$r16,\$r0 - 21c: 03 60 f0 45 45f06003 ldl.l \$r31,\$r0,0 - 220: 03 c0 0f 44 440fc003 ldl.l \$r0,\$r31,0 + 21c: 03 60 f0 45 45f06003 ldl.l \$r31,\$r0,200 + 220: 03 c0 0f 44 440fc003 ldl.l \$r0,\$r31,0 224: 13 c0 0f 44 440fc013 ldl.l \$r0,\$r31,1 228: f3 df 0f 44 440fdff3 ldl.l \$r0,\$r31,1ff 22c: 13 80 0f 42 420f8013 ldl.s \$r0,\$r31,\$r1 @@ -156,8 +156,8 @@ Disassembly of section .text: 244: fb 01 00 44 440001fb bins.l \$r0,\$r0,\$r31 248: 4b 00 11 44 4411004b bins.l \$r1,\$r2,\$r4 24c: 0b 00 88 44 4488000b bins.l \$r8,\$r16,\$r0 - 250: 0b 60 f0 45 45f0600b bins.l \$r31,\$r0,0 - 254: 0b c0 0f 44 440fc00b bins.l \$r0,\$r31,0 + 250: 0b 60 f0 45 45f0600b bins.l \$r31,\$r0,200 + 254: 0b c0 0f 44 440fc00b bins.l \$r0,\$r31,0 258: 1b c0 0f 44 440fc01b bins.l \$r0,\$r31,1 25c: fb df 0f 44 440fdffb bins.l \$r0,\$r31,1ff 260: 1b 80 0f 42 420f801b bins.s \$r0,\$r31,\$r1 @@ -169,8 +169,8 @@ Disassembly of section .text: 278: fc 01 00 44 440001fc bexts.l \$r0,\$r0,\$r31 27c: 4c 00 11 44 4411004c bexts.l \$r1,\$r2,\$r4 280: 0c 00 88 44 4488000c bexts.l \$r8,\$r16,\$r0 - 284: 0c 60 f0 45 45f0600c bexts.l \$r31,\$r0,0 - 288: 0c c0 0f 44 440fc00c bexts.l \$r0,\$r31,0 + 284: 0c 60 f0 45 45f0600c bexts.l \$r31,\$r0,200 + 288: 0c c0 0f 44 440fc00c bexts.l \$r0,\$r31,0 28c: 1c c0 0f 44 440fc01c bexts.l \$r0,\$r31,1 290: fc df 0f 44 440fdffc bexts.l \$r0,\$r31,1ff 294: 1c 80 0f 42 420f801c bexts.s \$r0,\$r31,\$r1 @@ -182,8 +182,8 @@ Disassembly of section .text: 2ac: fd 01 00 44 440001fd bextu.l \$r0,\$r0,\$r31 2b0: 4d 00 11 44 4411004d bextu.l \$r1,\$r2,\$r4 2b4: 0d 00 88 44 4488000d bextu.l \$r8,\$r16,\$r0 - 2b8: 0d 60 f0 45 45f0600d bextu.l \$r31,\$r0,0 - 2bc: 0d c0 0f 44 440fc00d bextu.l \$r0,\$r31,0 + 2b8: 0d 60 f0 45 45f0600d bextu.l \$r31,\$r0,200 + 2bc: 0d c0 0f 44 440fc00d bextu.l \$r0,\$r31,0 2c0: 1d c0 0f 44 440fc01d bextu.l \$r0,\$r31,1 2c4: fd df 0f 44 440fdffd bextu.l \$r0,\$r31,1ff 2c8: 1d 80 0f 42 420f801d bextu.s \$r0,\$r31,\$r1 @@ -195,8 +195,8 @@ Disassembly of section .text: 2e0: fe 01 00 44 440001fe flip.l \$r0,\$r0,\$r31 2e4: 4e 00 11 44 4411004e flip.l \$r1,\$r2,\$r4 2e8: 0e 00 88 44 4488000e flip.l \$r8,\$r16,\$r0 - 2ec: 0e 60 f0 45 45f0600e flip.l \$r31,\$r0,0 - 2f0: 0e c0 0f 44 440fc00e flip.l \$r0,\$r31,0 + 2ec: 0e 60 f0 45 45f0600e flip.l \$r31,\$r0,200 + 2f0: 0e c0 0f 44 440fc00e flip.l \$r0,\$r31,0 2f4: 1e c0 0f 44 440fc01e flip.l \$r0,\$r31,1 2f8: fe df 0f 44 440fdffe flip.l \$r0,\$r31,1ff 2fc: 1e 80 0f 42 420f801e flip.s \$r0,\$r31,\$r1 @@ -206,8 +206,8 @@ Disassembly of section .text: 30c: 00 00 e0 5d 5de00000 addcc.l \$r0,\$r0 310: 00 80 ef 5d 5def8000 addcc.l \$r31,\$r0 314: f0 01 e0 5d 5de001f0 addcc.l \$r0,\$r31 - 318: 00 60 e0 5d 5de06000 addcc.l \$r0,0 - 31c: 00 c0 ef 5d 5defc000 addcc.l \$r31,0 + 318: 00 60 e0 5d 5de06000 addcc.l \$r0,200 + 31c: 00 c0 ef 5d 5defc000 addcc.l \$r31,0 320: 10 c0 ef 5d 5defc010 addcc.l \$r31,1 324: f0 df ef 5d 5defdff0 addcc.l \$r31,1ff 328: 10 80 ef 5b 5bef8010 addcc.s \$r31,\$r1 @@ -217,8 +217,8 @@ Disassembly of section .text: 338: 02 00 e0 5d 5de00002 cmp.l \$r0,\$r0 33c: 02 80 ef 5d 5def8002 cmp.l \$r31,\$r0 340: f2 01 e0 5d 5de001f2 cmp.l \$r0,\$r31 - 344: 02 60 e0 5d 5de06002 cmp.l \$r0,0 - 348: 02 c0 ef 5d 5defc002 cmp.l \$r31,0 + 344: 02 60 e0 5d 5de06002 cmp.l \$r0,200 + 348: 02 c0 ef 5d 5defc002 cmp.l \$r31,0 34c: 12 c0 ef 5d 5defc012 cmp.l \$r31,1 350: f2 df ef 5d 5defdff2 cmp.l \$r31,1ff 354: 12 80 ef 5b 5bef8012 cmp.s \$r31,\$r1 @@ -228,8 +228,8 @@ Disassembly of section .text: 364: 04 00 e0 5d 5de00004 tst.l \$r0,\$r0 368: 04 80 ef 5d 5def8004 tst.l \$r31,\$r0 36c: f4 01 e0 5d 5de001f4 tst.l \$r0,\$r31 - 370: 04 60 e0 5d 5de06004 tst.l \$r0,0 - 374: 04 c0 ef 5d 5defc004 tst.l \$r31,0 + 370: 04 60 e0 5d 5de06004 tst.l \$r0,200 + 374: 04 c0 ef 5d 5defc004 tst.l \$r31,0 378: 14 c0 ef 5d 5defc014 tst.l \$r31,1 37c: f4 df ef 5d 5defdff4 tst.l \$r31,1ff 380: 14 80 ef 5b 5bef8014 tst.s \$r31,\$r1 @@ -239,8 +239,8 @@ Disassembly of section .text: 390: 0c 00 e0 5d 5de0000c btst.l \$r0,\$r0 394: 0c 80 ef 5d 5def800c btst.l \$r31,\$r0 398: fc 01 e0 5d 5de001fc btst.l \$r0,\$r31 - 39c: 0c 60 e0 5d 5de0600c btst.l \$r0,0 - 3a0: 0c c0 ef 5d 5defc00c btst.l \$r31,0 + 39c: 0c 60 e0 5d 5de0600c btst.l \$r0,200 + 3a0: 0c c0 ef 5d 5defc00c btst.l \$r31,0 3a4: 1c c0 ef 5d 5defc01c btst.l \$r31,1 3a8: fc df ef 5d 5defdffc btst.l \$r31,1ff 3ac: 1c 80 ef 5b 5bef801c btst.s \$r31,\$r1 @@ -265,27 +265,27 @@ Disassembly of section .text: 3f8: 7f 80 0f ea ea0f807f exi.s \$r0,\$r31,7f 3fc: 80 00 f0 e9 e9f00080 exi.b \$r31,\$r0,80 400: 7f 00 f0 e9 e9f0007f exi.b \$r31,\$r0,7f - 404: 00 00 00 6c 6c000000 lpm.l \$r0,0 - 408: 00 00 00 6b 6b000000 lpm.s \$r16,0 - 40c: 00 00 f0 69 69f00000 lpm.b \$r31,0 + 404: 00 00 00 6c 6c000000 lpm.l \$r0,0 + 408: 00 00 00 6b 6b000000 lpm.s \$r16,0 + 40c: 00 00 f0 69 69f00000 lpm.b \$r31,0 410: 80 80 00 cc cc008080 lpmi.l \$r0,\$r1,80 414: 7f 80 00 cb cb00807f lpmi.s \$r16,\$r1,7f 418: 80 80 f0 c9 c9f08080 lpmi.b \$r31,\$r1,80 - 41c: 00 00 30 00 00300000 jmp 0 + 41c: 00 00 30 00 00300000 jmp 0 420: 00 01 30 08 08300100 jmpi \$r16 - 424: 00 00 c8 07 07c80000 jmpx 31,\$r28,1,0 - 428: 00 00 20 00 00200000 jmpc nz,0 - 42c: 00 00 34 00 00340000 call 0 + 424: 00 00 c8 07 07c80000 jmpx 31,\$r28,1,0 + 428: 00 00 20 00 00200000 jmpc nz,0 + 42c: 00 00 34 00 00340000 call 0 430: 00 01 34 08 08340100 calli \$r16 - 434: 00 00 cc 07 07cc0000 callx 31,\$r28,1,0 - 438: 00 00 24 00 00240000 callc nz,0 + 434: 00 00 cc 07 07cc0000 callx 31,\$r28,1,0 + 438: 00 00 24 00 00240000 callc nz,0 43c: 00 00 00 84 84000000 push.l \$r0 440: 00 00 08 84 84080000 push.l \$r16 444: 00 80 0f 84 840f8000 push.l \$r31 448: 00 00 00 8c 8c000000 pop.l \$r0 44c: 00 00 00 8d 8d000000 pop.l \$r16 450: 00 00 f0 8d 8df00000 pop.l \$r31 - 454: 00 00 00 94 94000000 link \$r0,0 + 454: 00 00 00 94 94000000 link \$r0,0 458: ff ff 00 95 9500ffff link \$r16,ffff 45c: f9 03 f0 95 95f003f9 link \$r31,3f9 460: 00 00 00 98 98000000 unlink \$r0 @@ -293,18 +293,18 @@ Disassembly of section .text: 468: 00 00 f0 99 99f00000 unlink \$r31 46c: 00 00 00 a0 a0000000 return 470: 00 00 00 a4 a4000000 reti - 474: 00 00 00 c4 c4000000 lda.l \$r0,0 - 478: 00 00 00 c3 c3000000 lda.s \$r16,0 - 47c: 00 00 f0 c1 c1f00000 lda.b \$r31,0 - 480: 00 00 00 bc bc000000 sta.l 0 ,\$r0 - 484: 00 00 00 bb bb000000 sta.s 0 ,\$r16 - 488: 00 00 f0 b9 b9f00000 sta.b 0 ,\$r31 - 48c: 00 00 00 3c 3c000000 exa.l \$r0,0 - 490: 00 00 00 3b 3b000000 exa.s \$r16,0 - 494: 00 00 f0 39 39f00000 exa.b \$r31,0 + 474: 00 00 00 c4 c4000000 lda.l \$r0,0 + 478: 00 00 00 c3 c3000000 lda.s \$r16,0 + 47c: 00 00 f0 c1 c1f00000 lda.b \$r31,0 + 480: 00 00 00 bc bc000000 sta.l 0 ,\$r0 + 484: 00 00 00 bb bb000000 sta.s 0 ,\$r16 + 488: 00 00 f0 b9 b9f00000 sta.b 0 ,\$r31 + 48c: 00 00 00 3c 3c000000 exa.l \$r0,0 + 490: 00 00 00 3b 3b000000 exa.s \$r16,0 + 494: 00 00 f0 39 39f00000 exa.b \$r31,0 498: 00 00 08 64 64080000 ldk.l \$r0,80000 49c: ff ff 07 64 6407ffff ldk.l \$r0,7ffff - 4a0: 00 00 00 64 64000000 ldk.l \$r0,0 + 4a0: 00 00 00 64 64000000 ldk.l \$r0,0 4a4: 00 c0 0f 44 440fc000 move.l \$r0,\$r31 4a8: 00 40 f0 45 45f04000 move.l \$r31,\$r0 4ac: 00 00 f0 f5 f5f00000 udiv.l \$r31,\$r0,\$r0 @@ -312,8 +312,8 @@ Disassembly of section .text: 4b4: f0 01 00 f4 f40001f0 udiv.l \$r0,\$r0,\$r31 4b8: 40 00 11 f4 f4110040 udiv.l \$r1,\$r2,\$r4 4bc: 00 00 88 f4 f4880000 udiv.l \$r8,\$r16,\$r0 - 4c0: 00 60 f0 f5 f5f06000 udiv.l \$r31,\$r0,0 - 4c4: 00 c0 0f f4 f40fc000 udiv.l \$r0,\$r31,0 + 4c0: 00 60 f0 f5 f5f06000 udiv.l \$r31,\$r0,200 + 4c4: 00 c0 0f f4 f40fc000 udiv.l \$r0,\$r31,0 4c8: 10 c0 0f f4 f40fc010 udiv.l \$r0,\$r31,1 4cc: f0 df 0f f4 f40fdff0 udiv.l \$r0,\$r31,1ff 4d0: 10 80 0f f2 f20f8010 udiv.s \$r0,\$r31,\$r1 @@ -325,8 +325,8 @@ Disassembly of section .text: 4e8: f1 01 00 f4 f40001f1 umod.l \$r0,\$r0,\$r31 4ec: 41 00 11 f4 f4110041 umod.l \$r1,\$r2,\$r4 4f0: 01 00 88 f4 f4880001 umod.l \$r8,\$r16,\$r0 - 4f4: 01 60 f0 f5 f5f06001 umod.l \$r31,\$r0,0 - 4f8: 01 c0 0f f4 f40fc001 umod.l \$r0,\$r31,0 + 4f4: 01 60 f0 f5 f5f06001 umod.l \$r31,\$r0,200 + 4f8: 01 c0 0f f4 f40fc001 umod.l \$r0,\$r31,0 4fc: 11 c0 0f f4 f40fc011 umod.l \$r0,\$r31,1 500: f1 df 0f f4 f40fdff1 umod.l \$r0,\$r31,1ff 504: 11 80 0f f2 f20f8011 umod.s \$r0,\$r31,\$r1 @@ -338,8 +338,8 @@ Disassembly of section .text: 51c: f2 01 00 f4 f40001f2 div.l \$r0,\$r0,\$r31 520: 42 00 11 f4 f4110042 div.l \$r1,\$r2,\$r4 524: 02 00 88 f4 f4880002 div.l \$r8,\$r16,\$r0 - 528: 02 60 f0 f5 f5f06002 div.l \$r31,\$r0,0 - 52c: 02 c0 0f f4 f40fc002 div.l \$r0,\$r31,0 + 528: 02 60 f0 f5 f5f06002 div.l \$r31,\$r0,200 + 52c: 02 c0 0f f4 f40fc002 div.l \$r0,\$r31,0 530: 12 c0 0f f4 f40fc012 div.l \$r0,\$r31,1 534: f2 df 0f f4 f40fdff2 div.l \$r0,\$r31,1ff 538: 12 80 0f f2 f20f8012 div.s \$r0,\$r31,\$r1 @@ -351,8 +351,8 @@ Disassembly of section .text: 550: f3 01 00 f4 f40001f3 mod.l \$r0,\$r0,\$r31 554: 43 00 11 f4 f4110043 mod.l \$r1,\$r2,\$r4 558: 03 00 88 f4 f4880003 mod.l \$r8,\$r16,\$r0 - 55c: 03 60 f0 f5 f5f06003 mod.l \$r31,\$r0,0 - 560: 03 c0 0f f4 f40fc003 mod.l \$r0,\$r31,0 + 55c: 03 60 f0 f5 f5f06003 mod.l \$r31,\$r0,200 + 560: 03 c0 0f f4 f40fc003 mod.l \$r0,\$r31,0 564: 13 c0 0f f4 f40fc013 mod.l \$r0,\$r31,1 568: f3 df 0f f4 f40fdff3 mod.l \$r0,\$r31,1ff 56c: 13 80 0f f2 f20f8013 mod.s \$r0,\$r31,\$r1 @@ -364,8 +364,8 @@ Disassembly of section .text: 584: f4 01 00 f4 f40001f4 strcmp.l \$r0,\$r0,\$r31 588: 44 00 11 f4 f4110044 strcmp.l \$r1,\$r2,\$r4 58c: 04 00 88 f4 f4880004 strcmp.l \$r8,\$r16,\$r0 - 590: 04 60 f0 f5 f5f06004 strcmp.l \$r31,\$r0,0 - 594: 04 c0 0f f4 f40fc004 strcmp.l \$r0,\$r31,0 + 590: 04 60 f0 f5 f5f06004 strcmp.l \$r31,\$r0,200 + 594: 04 c0 0f f4 f40fc004 strcmp.l \$r0,\$r31,0 598: 14 c0 0f f4 f40fc014 strcmp.l \$r0,\$r31,1 59c: f4 df 0f f4 f40fdff4 strcmp.l \$r0,\$r31,1ff 5a0: 14 80 0f f2 f20f8014 strcmp.s \$r0,\$r31,\$r1 @@ -377,8 +377,8 @@ Disassembly of section .text: 5b8: f5 01 00 f4 f40001f5 memcpy.l \$r0,\$r0,\$r31 5bc: 45 00 11 f4 f4110045 memcpy.l \$r1,\$r2,\$r4 5c0: 05 00 88 f4 f4880005 memcpy.l \$r8,\$r16,\$r0 - 5c4: 05 60 f0 f5 f5f06005 memcpy.l \$r31,\$r0,0 - 5c8: 05 c0 0f f4 f40fc005 memcpy.l \$r0,\$r31,0 + 5c4: 05 60 f0 f5 f5f06005 memcpy.l \$r31,\$r0,200 + 5c8: 05 c0 0f f4 f40fc005 memcpy.l \$r0,\$r31,0 5cc: 15 c0 0f f4 f40fc015 memcpy.l \$r0,\$r31,1 5d0: f5 df 0f f4 f40fdff5 memcpy.l \$r0,\$r31,1ff 5d4: 15 80 0f f2 f20f8015 memcpy.s \$r0,\$r31,\$r1 @@ -390,8 +390,8 @@ Disassembly of section .text: 5ec: f7 01 00 f4 f40001f7 memset.l \$r0,\$r0,\$r31 5f0: 47 00 11 f4 f4110047 memset.l \$r1,\$r2,\$r4 5f4: 07 00 88 f4 f4880007 memset.l \$r8,\$r16,\$r0 - 5f8: 07 60 f0 f5 f5f06007 memset.l \$r31,\$r0,0 - 5fc: 07 c0 0f f4 f40fc007 memset.l \$r0,\$r31,0 + 5f8: 07 60 f0 f5 f5f06007 memset.l \$r31,\$r0,200 + 5fc: 07 c0 0f f4 f40fc007 memset.l \$r0,\$r31,0 600: 17 c0 0f f4 f40fc017 memset.l \$r0,\$r31,1 604: f7 df 0f f4 f40fdff7 memset.l \$r0,\$r31,1ff 608: 17 80 0f f2 f20f8017 memset.s \$r0,\$r31,\$r1 @@ -403,8 +403,8 @@ Disassembly of section .text: 620: f8 01 00 f4 f40001f8 mul.l \$r0,\$r0,\$r31 624: 48 00 11 f4 f4110048 mul.l \$r1,\$r2,\$r4 628: 08 00 88 f4 f4880008 mul.l \$r8,\$r16,\$r0 - 62c: 08 60 f0 f5 f5f06008 mul.l \$r31,\$r0,0 - 630: 08 c0 0f f4 f40fc008 mul.l \$r0,\$r31,0 + 62c: 08 60 f0 f5 f5f06008 mul.l \$r31,\$r0,200 + 630: 08 c0 0f f4 f40fc008 mul.l \$r0,\$r31,0 634: 18 c0 0f f4 f40fc018 mul.l \$r0,\$r31,1 638: f8 df 0f f4 f40fdff8 mul.l \$r0,\$r31,1ff 63c: 18 80 0f f2 f20f8018 mul.s \$r0,\$r31,\$r1 @@ -416,8 +416,8 @@ Disassembly of section .text: 654: f9 01 00 f4 f40001f9 muluh.l \$r0,\$r0,\$r31 658: 49 00 11 f4 f4110049 muluh.l \$r1,\$r2,\$r4 65c: 09 00 88 f4 f4880009 muluh.l \$r8,\$r16,\$r0 - 660: 09 60 f0 f5 f5f06009 muluh.l \$r31,\$r0,0 - 664: 09 c0 0f f4 f40fc009 muluh.l \$r0,\$r31,0 + 660: 09 60 f0 f5 f5f06009 muluh.l \$r31,\$r0,200 + 664: 09 c0 0f f4 f40fc009 muluh.l \$r0,\$r31,0 668: 19 c0 0f f4 f40fc019 muluh.l \$r0,\$r31,1 66c: f9 df 0f f4 f40fdff9 muluh.l \$r0,\$r31,1ff 670: 19 80 0f f2 f20f8019 muluh.s \$r0,\$r31,\$r1 @@ -429,8 +429,8 @@ Disassembly of section .text: 688: fc 01 00 f4 f40001fc streamin.l \$r0,\$r0,\$r31 68c: 4c 00 11 f4 f411004c streamin.l \$r1,\$r2,\$r4 690: 0c 00 88 f4 f488000c streamin.l \$r8,\$r16,\$r0 - 694: 0c 60 f0 f5 f5f0600c streamin.l \$r31,\$r0,0 - 698: 0c c0 0f f4 f40fc00c streamin.l \$r0,\$r31,0 + 694: 0c 60 f0 f5 f5f0600c streamin.l \$r31,\$r0,200 + 698: 0c c0 0f f4 f40fc00c streamin.l \$r0,\$r31,0 69c: 1c c0 0f f4 f40fc01c streamin.l \$r0,\$r31,1 6a0: fc df 0f f4 f40fdffc streamin.l \$r0,\$r31,1ff 6a4: 1c 80 0f f2 f20f801c streamin.s \$r0,\$r31,\$r1 @@ -442,8 +442,8 @@ Disassembly of section .text: 6bc: fd 01 00 f4 f40001fd streamini.l \$r0,\$r0,\$r31 6c0: 4d 00 11 f4 f411004d streamini.l \$r1,\$r2,\$r4 6c4: 0d 00 88 f4 f488000d streamini.l \$r8,\$r16,\$r0 - 6c8: 0d 60 f0 f5 f5f0600d streamini.l \$r31,\$r0,0 - 6cc: 0d c0 0f f4 f40fc00d streamini.l \$r0,\$r31,0 + 6c8: 0d 60 f0 f5 f5f0600d streamini.l \$r31,\$r0,200 + 6cc: 0d c0 0f f4 f40fc00d streamini.l \$r0,\$r31,0 6d0: 1d c0 0f f4 f40fc01d streamini.l \$r0,\$r31,1 6d4: fd df 0f f4 f40fdffd streamini.l \$r0,\$r31,1ff 6d8: 1d 80 0f f2 f20f801d streamini.s \$r0,\$r31,\$r1 @@ -455,8 +455,8 @@ Disassembly of section .text: 6f0: fe 01 00 f4 f40001fe streamout.l \$r0,\$r0,\$r31 6f4: 4e 00 11 f4 f411004e streamout.l \$r1,\$r2,\$r4 6f8: 0e 00 88 f4 f488000e streamout.l \$r8,\$r16,\$r0 - 6fc: 0e 60 f0 f5 f5f0600e streamout.l \$r31,\$r0,0 - 700: 0e c0 0f f4 f40fc00e streamout.l \$r0,\$r31,0 + 6fc: 0e 60 f0 f5 f5f0600e streamout.l \$r31,\$r0,200 + 700: 0e c0 0f f4 f40fc00e streamout.l \$r0,\$r31,0 704: 1e c0 0f f4 f40fc01e streamout.l \$r0,\$r31,1 708: fe df 0f f4 f40fdffe streamout.l \$r0,\$r31,1ff 70c: 1e 80 0f f2 f20f801e streamout.s \$r0,\$r31,\$r1 @@ -468,8 +468,8 @@ Disassembly of section .text: 724: ff 01 00 f4 f40001ff streamouti.l \$r0,\$r0,\$r31 728: 4f 00 11 f4 f411004f streamouti.l \$r1,\$r2,\$r4 72c: 0f 00 88 f4 f488000f streamouti.l \$r8,\$r16,\$r0 - 730: 0f 60 f0 f5 f5f0600f streamouti.l \$r31,\$r0,0 - 734: 0f c0 0f f4 f40fc00f streamouti.l \$r0,\$r31,0 + 730: 0f 60 f0 f5 f5f0600f streamouti.l \$r31,\$r0,200 + 734: 0f c0 0f f4 f40fc00f streamouti.l \$r0,\$r31,0 738: 1f c0 0f f4 f40fc01f streamouti.l \$r0,\$r31,1 73c: ff df 0f f4 f40fdfff streamouti.l \$r0,\$r31,1ff 740: 1f 80 0f f2 f20f801f streamouti.s \$r0,\$r31,\$r1 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index e7073e0dea3..c63e81b30cf 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -490,7 +490,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-addr32-intel" run_dump_test "x86-64-opcode" run_dump_test "x86-64-intel64" - if { ![istarget "*-*-mingw*"] } then { + if { ! [istarget "*-*-*cygwin*"] && ![istarget "*-*-mingw*"] } then { run_dump_test "x86-64-pcrel" run_dump_test "x86-64-disassem" } else { diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp index 567db672cfb..81e0396740c 100644 --- a/gas/testsuite/gas/lns/lns.exp +++ b/gas/testsuite/gas/lns/lns.exp @@ -27,8 +27,6 @@ run_dump_test "lns-duplicate" if { ![istarget i370-*-*] && ![istarget i960-*-*] - && ![istarget mcore-*-*] - && ![istarget rx-*-*] && ![istarget s390*-*-*] } { # Use alternate file for targets using DW_LNS_fixed_advance_pc opcodes. diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp index 096e62ee901..612258d4c5c 100644 --- a/gas/testsuite/gas/macros/macros.exp +++ b/gas/testsuite/gas/macros/macros.exp @@ -78,10 +78,14 @@ case $target_triplet in { { *c54x*-*-* } { } { *c4x*-*-* } { } { mmix-* } { } + { ns32k-*-* } { } + { rl78-*-* } { } { rx-*-* } { } + { vax-*-* } { } default { run_list_test dot "-alm" } } run_list_test end "" +setup_xfail "ns32k-*-*" "vax-*-*" run_list_test purge "--hash-size=8000" run_list_test redef "" diff --git a/gas/testsuite/gas/nds32/alu-2.d b/gas/testsuite/gas/nds32/alu-2.d index 11c2eb1652b..68292ff7a37 100644 --- a/gas/testsuite/gas/nds32/alu-2.d +++ b/gas/testsuite/gas/nds32/alu-2.d @@ -32,7 +32,7 @@ Disassembly of section .text: 0+0058 <[^>]*> bse \$r0, \$r1, \$r2 0+005c <[^>]*> bsp \$r0, \$r1, \$r2 0+0060 <[^>]*> ffb \$r0, \$r1, \$r2 -0+0064 <[^>]*> ffbi \$r0, \$r1, #0x8 +0+0064 <[^>]*> ffbi \$r0, \$r1, #1 0+0068 <[^>]*> ffmism \$r0, \$r1, \$r2 0+006c <[^>]*> flmism \$r0, \$r1, \$r2 0+0070 <[^>]*> maddr32 \$r0, \$r0, \$r1 diff --git a/gas/testsuite/gas/nds32/ls.d b/gas/testsuite/gas/nds32/ls.d index 688ed11b4f6..c9c988550a7 100644 --- a/gas/testsuite/gas/nds32/ls.d +++ b/gas/testsuite/gas/nds32/ls.d @@ -7,19 +7,19 @@ .*: file format .* Disassembly of section .text: -0+0000 <[^>]*> lw \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0004 <[^>]*> lh \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0008 <[^>]*> lhs \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+000c <[^>]*> lb \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0010 <[^>]*> lbs \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0014 <[^>]*> sw \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0018 <[^>]*> sh \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+001c <[^>]*> sb \$r0, \[\$r1 \+ \(\$r2 << 1\)\] -0+0020 <[^>]*> lw.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+0024 <[^>]*> lh.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+0028 <[^>]*> lhs.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+002c <[^>]*> lb.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+0030 <[^>]*> lbs.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+0034 <[^>]*> sw.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+0038 <[^>]*> sh.bi \$r0, \[\$r1\], \(\$r2 << 1\) -0+003c <[^>]*> sb.bi \$r0, \[\$r1\], \(\$r2 << 1\) +0+0000 <[^>]*> lw \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0004 <[^>]*> lh \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0008 <[^>]*> lhs \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+000c <[^>]*> lb \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0010 <[^>]*> lbs \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0014 <[^>]*> sw \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0018 <[^>]*> sh \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+001c <[^>]*> sb \$r0, \[\$r1 \+ \(\$r2 << #1\)\] +0+0020 <[^>]*> lw.bi \$r0, \[\$r1\], \$r2 << #1 +0+0024 <[^>]*> lh.bi \$r0, \[\$r1\], \$r2 << #1 +0+0028 <[^>]*> lhs.bi \$r0, \[\$r1\], \$r2 << #1 +0+002c <[^>]*> lb.bi \$r0, \[\$r1\], \$r2 << #1 +0+0030 <[^>]*> lbs.bi \$r0, \[\$r1\], \$r2 << #1 +0+0034 <[^>]*> sw.bi \$r0, \[\$r1\], \$r2 << #1 +0+0038 <[^>]*> sh.bi \$r0, \[\$r1\], \$r2 << #1 +0+003c <[^>]*> sb.bi \$r0, \[\$r1\], \$r2 << #1 diff --git a/gas/testsuite/gas/nds32/sys-reg.d b/gas/testsuite/gas/nds32/sys-reg.d index 0a3b6340603..08249600ca5 100644 --- a/gas/testsuite/gas/nds32/sys-reg.d +++ b/gas/testsuite/gas/nds32/sys-reg.d @@ -8,111 +8,111 @@ Disassembly of section .text: -0+0000 <[^>]*> mfsr \$r0, \$CPU_VER -0+0004 <[^>]*> mfsr \$r0, \$CORE_ID -0+0008 <[^>]*> mfsr \$r0, \$ICM_CFG -0+000c <[^>]*> mfsr \$r0, \$DCM_CFG -0+0010 <[^>]*> mfsr \$r0, \$MMU_CFG -0+0014 <[^>]*> mfsr \$r0, \$MSC_CFG -0+0018 <[^>]*> mfsr \$r0, \$PSW -0+001c <[^>]*> mfsr \$r0, \$IPSW -0+0020 <[^>]*> mfsr \$r0, \$P_IPSW -0+0024 <[^>]*> mfsr \$r0, \$IVB -0+0028 <[^>]*> mfsr \$r0, \$INT_CTRL -0+002c <[^>]*> mfsr \$r0, \$EVA -0+0030 <[^>]*> mfsr \$r0, \$P_EVA -0+0034 <[^>]*> mfsr \$r0, \$ITYPE -0+0038 <[^>]*> mfsr \$r0, \$P_ITYPE -0+003c <[^>]*> mfsr \$r0, \$MERR -0+0040 <[^>]*> mfsr \$r0, \$IPC -0+0044 <[^>]*> mfsr \$r0, \$P_IPC -0+0048 <[^>]*> mfsr \$r0, \$OIPC -0+004c <[^>]*> mfsr \$r0, \$P_P0 -0+0050 <[^>]*> mfsr \$r0, \$P_P1 -0+0054 <[^>]*> mfsr \$r0, \$INT_MASK -0+0058 <[^>]*> mfsr \$r0, \$INT_MASK2 -0+005c <[^>]*> mfsr \$r0, \$INT_PEND -0+0060 <[^>]*> mfsr \$r0, \$INT_PEND2 -0+0064 <[^>]*> mfsr \$r0, \$INT_TRIGGER -0+0068 <[^>]*> mfsr \$r0, \$SP_USR -0+006c <[^>]*> mfsr \$r0, \$SP_PRIV -0+0070 <[^>]*> mfsr \$r0, \$INT_PRI -0+0074 <[^>]*> mfsr \$r0, \$INT_PRI2 -0+0078 <[^>]*> mfsr \$r0, \$MMU_CTL -0+007c <[^>]*> mfsr \$r0, \$L1_PPTB -0+0080 <[^>]*> mfsr \$r0, \$TLB_VPN -0+0084 <[^>]*> mfsr \$r0, \$TLB_DATA -0+0088 <[^>]*> mfsr \$r0, \$TLB_MISC -0+008c <[^>]*> mfsr \$r0, \$VLPT_IDX -0+0090 <[^>]*> mfsr \$r0, \$ILMB -0+0094 <[^>]*> mfsr \$r0, \$DLMB -0+0098 <[^>]*> mfsr \$r0, \$CACHE_CTL -0+009c <[^>]*> mfsr \$r0, \$HSMP_SADDR -0+00a0 <[^>]*> mfsr \$r0, \$HSMP_EADDR -0+00a4 <[^>]*> mfsr \$r0, \$SDZ_CTL -0+00a8 <[^>]*> mfsr \$r0, \$MISC_CTL -0+00ac <[^>]*> mfsr \$r0, \$BPC0 -0+00b0 <[^>]*> mfsr \$r0, \$BPC1 -0+00b4 <[^>]*> mfsr \$r0, \$BPC2 -0+00b8 <[^>]*> mfsr \$r0, \$BPC3 -0+00bc <[^>]*> mfsr \$r0, \$BPC4 -0+00c0 <[^>]*> mfsr \$r0, \$BPC5 -0+00c4 <[^>]*> mfsr \$r0, \$BPC6 -0+00c8 <[^>]*> mfsr \$r0, \$BPC7 -0+00cc <[^>]*> mfsr \$r0, \$BPA0 -0+00d0 <[^>]*> mfsr \$r0, \$BPA1 -0+00d4 <[^>]*> mfsr \$r0, \$BPA2 -0+00d8 <[^>]*> mfsr \$r0, \$BPA3 -0+00dc <[^>]*> mfsr \$r0, \$BPA4 -0+00e0 <[^>]*> mfsr \$r0, \$BPA5 -0+00e4 <[^>]*> mfsr \$r0, \$BPA6 -0+00e8 <[^>]*> mfsr \$r0, \$BPA7 -0+00ec <[^>]*> mfsr \$r0, \$BPAM0 -0+00f0 <[^>]*> mfsr \$r0, \$BPAM1 -0+00f4 <[^>]*> mfsr \$r0, \$BPAM2 -0+00f8 <[^>]*> mfsr \$r0, \$BPAM3 -0+00fc <[^>]*> mfsr \$r0, \$BPAM4 -0+0100 <[^>]*> mfsr \$r0, \$BPAM5 -0+0104 <[^>]*> mfsr \$r0, \$BPAM6 -0+0108 <[^>]*> mfsr \$r0, \$BPAM7 -0+010c <[^>]*> mfsr \$r0, \$BPV0 -0+0110 <[^>]*> mfsr \$r0, \$BPV1 -0+0114 <[^>]*> mfsr \$r0, \$BPV2 -0+0118 <[^>]*> mfsr \$r0, \$BPV3 -0+011c <[^>]*> mfsr \$r0, \$BPV4 -0+0120 <[^>]*> mfsr \$r0, \$BPV5 -0+0124 <[^>]*> mfsr \$r0, \$BPV6 -0+0128 <[^>]*> mfsr \$r0, \$BPV7 -0+012c <[^>]*> mfsr \$r0, \$BPCID0 -0+0130 <[^>]*> mfsr \$r0, \$BPCID1 -0+0134 <[^>]*> mfsr \$r0, \$BPCID2 -0+0138 <[^>]*> mfsr \$r0, \$BPCID3 -0+013c <[^>]*> mfsr \$r0, \$BPCID4 -0+0140 <[^>]*> mfsr \$r0, \$BPCID5 -0+0144 <[^>]*> mfsr \$r0, \$BPCID6 -0+0148 <[^>]*> mfsr \$r0, \$BPCID7 -0+014c <[^>]*> mfsr \$r0, \$EDM_CFG -0+0150 <[^>]*> mfsr \$r0, \$EDMSW -0+0154 <[^>]*> mfsr \$r0, \$EDM_CTL -0+0158 <[^>]*> mfsr \$r0, \$EDM_DTR -0+015c <[^>]*> mfsr \$r0, \$BPMTC -0+0160 <[^>]*> mfsr \$r0, \$DIMBR -0+0164 <[^>]*> mfsr \$r0, \$TECR0 -0+0168 <[^>]*> mfsr \$r0, \$TECR1 -0+016c <[^>]*> mfsr \$r0, \$PFMC0 -0+0170 <[^>]*> mfsr \$r0, \$PFMC1 -0+0174 <[^>]*> mfsr \$r0, \$PFMC2 -0+0178 <[^>]*> mfsr \$r0, \$PFM_CTL -0+017c <[^>]*> mfsr \$r0, \$PRUSR_ACC_CTL -0+0180 <[^>]*> mfsr \$r0, \$FUCOP_CTL -0+0184 <[^>]*> mfsr \$r0, \$DMA_CFG -0+0188 <[^>]*> mfsr \$r0, \$DMA_GCSW -0+018c <[^>]*> mfsr \$r0, \$DMA_CHNSEL -0+0190 <[^>]*> mfsr \$r0, \$DMA_ACT -0+0194 <[^>]*> mfsr \$r0, \$DMA_SETUP -0+0198 <[^>]*> mfsr \$r0, \$DMA_ISADDR -0+019c <[^>]*> mfsr \$r0, \$DMA_ESADDR -0+01a0 <[^>]*> mfsr \$r0, \$DMA_TCNT -0+01a4 <[^>]*> mfsr \$r0, \$DMA_STATUS -0+01a8 <[^>]*> mfsr \$r0, \$DMA_2DSET -0+01ac <[^>]*> mfsr \$r0, \$DMA_2DSCTL +0+0000 <[^>]*> mfsr \$r0, \$cpu_ver +0+0004 <[^>]*> mfsr \$r0, \$core_id +0+0008 <[^>]*> mfsr \$r0, \$icm_cfg +0+000c <[^>]*> mfsr \$r0, \$dcm_cfg +0+0010 <[^>]*> mfsr \$r0, \$mmu_cfg +0+0014 <[^>]*> mfsr \$r0, \$msc_cfg +0+0018 <[^>]*> mfsr \$r0, \$psw +0+001c <[^>]*> mfsr \$r0, \$ipsw +0+0020 <[^>]*> mfsr \$r0, \$p_ipsw +0+0024 <[^>]*> mfsr \$r0, \$ivb +0+0028 <[^>]*> mfsr \$r0, \$int_ctrl +0+002c <[^>]*> mfsr \$r0, \$eva +0+0030 <[^>]*> mfsr \$r0, \$p_eva +0+0034 <[^>]*> mfsr \$r0, \$itype +0+0038 <[^>]*> mfsr \$r0, \$p_itype +0+003c <[^>]*> mfsr \$r0, \$merr +0+0040 <[^>]*> mfsr \$r0, \$ipc +0+0044 <[^>]*> mfsr \$r0, \$p_ipc +0+0048 <[^>]*> mfsr \$r0, \$oipc +0+004c <[^>]*> mfsr \$r0, \$p_p0 +0+0050 <[^>]*> mfsr \$r0, \$p_p1 +0+0054 <[^>]*> mfsr \$r0, \$int_mask +0+0058 <[^>]*> mfsr \$r0, \$int_mask2 +0+005c <[^>]*> mfsr \$r0, \$int_pend +0+0060 <[^>]*> mfsr \$r0, \$int_pend2 +0+0064 <[^>]*> mfsr \$r0, \$int_trigger +0+0068 <[^>]*> mfsr \$r0, \$sp_usr +0+006c <[^>]*> mfsr \$r0, \$sp_priv +0+0070 <[^>]*> mfsr \$r0, \$int_pri +0+0074 <[^>]*> mfsr \$r0, \$int_pri2 +0+0078 <[^>]*> mfsr \$r0, \$mmu_ctl +0+007c <[^>]*> mfsr \$r0, \$l1_pptb +0+0080 <[^>]*> mfsr \$r0, \$tlb_vpn +0+0084 <[^>]*> mfsr \$r0, \$tlb_data +0+0088 <[^>]*> mfsr \$r0, \$tlb_misc +0+008c <[^>]*> mfsr \$r0, \$vlpt_idx +0+0090 <[^>]*> mfsr \$r0, \$ilmb +0+0094 <[^>]*> mfsr \$r0, \$dlmb +0+0098 <[^>]*> mfsr \$r0, \$cache_ctl +0+009c <[^>]*> mfsr \$r0, \$hsmp_saddr +0+00a0 <[^>]*> mfsr \$r0, \$hsmp_eaddr +0+00a4 <[^>]*> mfsr \$r0, \$sdz_ctl +0+00a8 <[^>]*> mfsr \$r0, \$misc_ctl +0+00ac <[^>]*> mfsr \$r0, \$bpc0 +0+00b0 <[^>]*> mfsr \$r0, \$bpc1 +0+00b4 <[^>]*> mfsr \$r0, \$bpc2 +0+00b8 <[^>]*> mfsr \$r0, \$bpc3 +0+00bc <[^>]*> mfsr \$r0, \$bpc4 +0+00c0 <[^>]*> mfsr \$r0, \$bpc5 +0+00c4 <[^>]*> mfsr \$r0, \$bpc6 +0+00c8 <[^>]*> mfsr \$r0, \$bpc7 +0+00cc <[^>]*> mfsr \$r0, \$bpa0 +0+00d0 <[^>]*> mfsr \$r0, \$bpa1 +0+00d4 <[^>]*> mfsr \$r0, \$bpa2 +0+00d8 <[^>]*> mfsr \$r0, \$bpa3 +0+00dc <[^>]*> mfsr \$r0, \$bpa4 +0+00e0 <[^>]*> mfsr \$r0, \$bpa5 +0+00e4 <[^>]*> mfsr \$r0, \$bpa6 +0+00e8 <[^>]*> mfsr \$r0, \$bpa7 +0+00ec <[^>]*> mfsr \$r0, \$bpam0 +0+00f0 <[^>]*> mfsr \$r0, \$bpam1 +0+00f4 <[^>]*> mfsr \$r0, \$bpam2 +0+00f8 <[^>]*> mfsr \$r0, \$bpam3 +0+00fc <[^>]*> mfsr \$r0, \$bpam4 +0+0100 <[^>]*> mfsr \$r0, \$bpam5 +0+0104 <[^>]*> mfsr \$r0, \$bpam6 +0+0108 <[^>]*> mfsr \$r0, \$bpam7 +0+010c <[^>]*> mfsr \$r0, \$bpv0 +0+0110 <[^>]*> mfsr \$r0, \$bpv1 +0+0114 <[^>]*> mfsr \$r0, \$bpv2 +0+0118 <[^>]*> mfsr \$r0, \$bpv3 +0+011c <[^>]*> mfsr \$r0, \$bpv4 +0+0120 <[^>]*> mfsr \$r0, \$bpv5 +0+0124 <[^>]*> mfsr \$r0, \$bpv6 +0+0128 <[^>]*> mfsr \$r0, \$bpv7 +0+012c <[^>]*> mfsr \$r0, \$bpcid0 +0+0130 <[^>]*> mfsr \$r0, \$bpcid1 +0+0134 <[^>]*> mfsr \$r0, \$bpcid2 +0+0138 <[^>]*> mfsr \$r0, \$bpcid3 +0+013c <[^>]*> mfsr \$r0, \$bpcid4 +0+0140 <[^>]*> mfsr \$r0, \$bpcid5 +0+0144 <[^>]*> mfsr \$r0, \$bpcid6 +0+0148 <[^>]*> mfsr \$r0, \$bpcid7 +0+014c <[^>]*> mfsr \$r0, \$edm_cfg +0+0150 <[^>]*> mfsr \$r0, \$edmsw +0+0154 <[^>]*> mfsr \$r0, \$edm_ctl +0+0158 <[^>]*> mfsr \$r0, \$edm_dtr +0+015c <[^>]*> mfsr \$r0, \$bpmtc +0+0160 <[^>]*> mfsr \$r0, \$dimbr +0+0164 <[^>]*> mfsr \$r0, \$tecr0 +0+0168 <[^>]*> mfsr \$r0, \$tecr1 +0+016c <[^>]*> mfsr \$r0, \$pfmc0 +0+0170 <[^>]*> mfsr \$r0, \$pfmc1 +0+0174 <[^>]*> mfsr \$r0, \$pfmc2 +0+0178 <[^>]*> mfsr \$r0, \$pfm_ctl +0+017c <[^>]*> mfsr \$r0, \$prusr_acc_ctl +0+0180 <[^>]*> mfsr \$r0, \$fucpr +0+0184 <[^>]*> mfsr \$r0, \$dma_cfg +0+0188 <[^>]*> mfsr \$r0, \$dma_gcsw +0+018c <[^>]*> mfsr \$r0, \$dma_chnsel +0+0190 <[^>]*> mfsr \$r0, \$dma_act +0+0194 <[^>]*> mfsr \$r0, \$dma_setup +0+0198 <[^>]*> mfsr \$r0, \$dma_isaddr +0+019c <[^>]*> mfsr \$r0, \$dma_esaddr +0+01a0 <[^>]*> mfsr \$r0, \$dma_tcnt +0+01a4 <[^>]*> mfsr \$r0, \$dma_status +0+01a8 <[^>]*> mfsr \$r0, \$dma_2dset +0+01ac <[^>]*> mfsr \$r0, \$dma_2dsctl diff --git a/gas/testsuite/gas/nds32/usr-spe-reg.d b/gas/testsuite/gas/nds32/usr-spe-reg.d index 6ff6d969341..b3bad804d9d 100644 --- a/gas/testsuite/gas/nds32/usr-spe-reg.d +++ b/gas/testsuite/gas/nds32/usr-spe-reg.d @@ -12,18 +12,18 @@ Disassembly of section .text: 0+0008 <[^>]*> mfusr \$r0, \$d1.lo 0+000c <[^>]*> mfusr \$r0, \$d1.hi 0+0010 <[^>]*> mfusr \$r0, \$pc -0+0014 <[^>]*> mfusr \$r0, \$DMA_CFG -0+0018 <[^>]*> mfusr \$r0, \$DMA_GCSW -0+001c <[^>]*> mfusr \$r0, \$DMA_CHNSEL -0+0020 <[^>]*> mfusr \$r0, \$DMA_ACT -0+0024 <[^>]*> mfusr \$r0, \$DMA_SETUP -0+0028 <[^>]*> mfusr \$r0, \$DMA_ISADDR -0+002c <[^>]*> mfusr \$r0, \$DMA_ESADDR -0+0030 <[^>]*> mfusr \$r0, \$DMA_TCNT -0+0034 <[^>]*> mfusr \$r0, \$DMA_STATUS -0+0038 <[^>]*> mfusr \$r0, \$DMA_2DSET -0+003c <[^>]*> mfusr \$r0, \$DMA_2DSCTL -0+0040 <[^>]*> mfusr \$r0, \$PFMC0 -0+0044 <[^>]*> mfusr \$r0, \$PFMC1 -0+0048 <[^>]*> mfusr \$r0, \$PFMC2 -0+004c <[^>]*> mfusr \$r0, \$PFM_CTL +0+0014 <[^>]*> mfusr \$r0, \$dma_cfg +0+0018 <[^>]*> mfusr \$r0, \$dma_gcsw +0+001c <[^>]*> mfusr \$r0, \$dma_chnsel +0+0020 <[^>]*> mfusr \$r0, \$dma_act +0+0024 <[^>]*> mfusr \$r0, \$dma_setup +0+0028 <[^>]*> mfusr \$r0, \$dma_isaddr +0+002c <[^>]*> mfusr \$r0, \$dma_esaddr +0+0030 <[^>]*> mfusr \$r0, \$dma_tcnt +0+0034 <[^>]*> mfusr \$r0, \$dma_status +0+0038 <[^>]*> mfusr \$r0, \$dma_2dset +0+003c <[^>]*> mfusr \$r0, \$dma_2dsctl +0+0040 <[^>]*> mfusr \$r0, \$pfmc0 +0+0044 <[^>]*> mfusr \$r0, \$pfmc1 +0+0048 <[^>]*> mfusr \$r0, \$pfmc2 +0+004c <[^>]*> mfusr \$r0, \$pfm_ctl diff --git a/gas/testsuite/gas/pe/aligncomm-d.d b/gas/testsuite/gas/pe/aligncomm-d.d index 05066fb29ed..b7ebbf67444 100644 --- a/gas/testsuite/gas/pe/aligncomm-d.d +++ b/gas/testsuite/gas/pe/aligncomm-d.d @@ -10,4 +10,4 @@ Contents of section .drectve: 0010 2c38202d 616c6967 6e636f6d 6d3a225f ,8 -aligncomm:"_ 0020 69222c34 202d616c 69676e63 6f6d6d3a i",4 -aligncomm: 0030 225f6a22 2c32202d 616c6967 6e636f6d "_j",2 -aligncom - 0040 6d3a225f 6b222c31 m:"_k",1.* + 0040 6d3a225f 6b222c31 ........ ........ m:"_k",1.* diff --git a/gas/testsuite/gas/pe/section-align-1.d b/gas/testsuite/gas/pe/section-align-1.d index 908bc37e1f5..a37525322b4 100644 --- a/gas/testsuite/gas/pe/section-align-1.d +++ b/gas/testsuite/gas/pe/section-align-1.d @@ -1,5 +1,6 @@ #objdump: -h #name: section alignment +#skip: sh-* # Test that alignment works in .section directives. diff --git a/gas/testsuite/gas/pe/section-align-3.d b/gas/testsuite/gas/pe/section-align-3.d index 5a8c2ad31d3..848968823b7 100644 --- a/gas/testsuite/gas/pe/section-align-3.d +++ b/gas/testsuite/gas/pe/section-align-3.d @@ -1,5 +1,6 @@ #objdump: -h #name: section alignment +#skip: sh-* # Test that alignment works in .section directives. diff --git a/gas/testsuite/gas/pe/section-exclude.d b/gas/testsuite/gas/pe/section-exclude.d index 039ef265099..b6c9918efa4 100644 --- a/gas/testsuite/gas/pe/section-exclude.d +++ b/gas/testsuite/gas/pe/section-exclude.d @@ -1,5 +1,6 @@ #objdump: -h #name: section exclude +#skip: sh-* # Test that 'e' works in .section directives. diff --git a/gas/testsuite/gas/ppc/test2xcoff32.d b/gas/testsuite/gas/ppc/test2xcoff32.d index 125d34a198f..71f2d07d954 100644 --- a/gas/testsuite/gas/ppc/test2xcoff32.d +++ b/gas/testsuite/gas/ppc/test2xcoff32.d @@ -37,4 +37,4 @@ Disassembly of section .text: 00000060 <_t\.rw_>: 60: 25 64 0a 00 dozi r11,r4,2560 - ... +#pass diff --git a/gas/testsuite/gas/ppc/textalign-xcoff-001.d b/gas/testsuite/gas/ppc/textalign-xcoff-001.d index 2bd6e8dfdb8..f8bf2650587 100644 --- a/gas/testsuite/gas/ppc/textalign-xcoff-001.d +++ b/gas/testsuite/gas/ppc/textalign-xcoff-001.d @@ -5,7 +5,7 @@ .*: file format aixcoff-rs6000 Sections: -Idx Name Size VMA LMA File off Algn +Idx[ ]+Name[ ]+Size[ ]+VMA[ ]+LMA[ ]+File off[ ]+Algn 0 \.text 00000004 0+0 0+0 000000a8 2\*\*2 CONTENTS, ALLOC, LOAD, CODE 1 \.data 00000008 0+08 0+08 000000ac 2\*\*3 diff --git a/gas/testsuite/gas/tilepro/t_constants.d b/gas/testsuite/gas/tilepro/t_constants.d index c3ee25f48e7..95eaddf52e5 100644 --- a/gas/testsuite/gas/tilepro/t_constants.d +++ b/gas/testsuite/gas/tilepro/t_constants.d @@ -247,16 +247,5 @@ Contents of section .data: 0f00 dadae7ab 0d5f5ece 0d5f5ece 00000000 .* 0f10 00000000 00000000 00000000 00000000 .* 0f20 00000000 00000000 00000000 00000000 .* - 0f30 00000000 00000000 00000000 00000000 .* - 0f40 00000000 00000000 00000000 00000000 .* - 0f50 00000000 00000000 00000000 00000000 .* - 0f60 00000000 00000000 00000000 00000000 .* - 0f70 00000000 00000000 00000000 00000000 .* - 0f80 00000000 00000000 00000000 00000000 .* - 0f90 00000000 00000000 00000000 00000000 .* - 0fa0 00000000 00000000 00000000 00000000 .* - 0fb0 00000000 00000000 00000000 00000000 .* - 0fc0 00000000 00000000 00000000 00000000 .* - 0fd0 00000000 00000000 00000000 00000000 .* - 0fe0 00000000 00000000 00000000 00000000 .* - 0ff0 00000000 00000000 00000000 00000000 .* + 0f30 00000000 .* +#pass diff --git a/gas/testsuite/gas/tilepro/t_constants.s b/gas/testsuite/gas/tilepro/t_constants.s index bf36a2501f0..fc9e1db56c0 100644 --- a/gas/testsuite/gas/tilepro/t_constants.s +++ b/gas/testsuite/gas/tilepro/t_constants.s @@ -244,385 +244,390 @@ label_2: .word 19388681 - 272825489 + -1311808516 .word -1311808516 - (272825489 - 19388681) .int 19338670 + 260459768 - .word 19338670 - 260459768 + -1967857243 - .word -1967857243 - (260459768 - 19338670) + +.macro .safe_word val + .word (\val) & 0xffffffff +.endm + + .safe_word 19338670 - 260459768 + -1967857243 + .safe_word -1967857243 - (260459768 - 19338670) .int 28605974 + 396753564 - .word 28605974 - 396753564 + 370199 - .word 370199 - (396753564 - 28605974) + .safe_word 28605974 - 396753564 + 370199 + .safe_word 370199 - (396753564 - 28605974) .int 28554816 + 378218842 - .word 28554816 - 378218842 + -665394889 - .word -665394889 - (378218842 - 28554816) + .safe_word 28554816 - 378218842 + -665394889 + .safe_word -665394889 - (378218842 - 28554816) .int 28503658 + 359684120 - .word 28503658 - 359684120 + -1331159977 - .word -1331159977 - (359684120 - 28503658) + .safe_word 28503658 - 359684120 + -1331159977 + .safe_word -1331159977 - (359684120 - 28503658) .int 28452500 + 341149398 - .word 28452500 - 341149398 + -1996925065 - .word -1996925065 - (341149398 - 28452500) + .safe_word 28452500 - 341149398 + -1996925065 + .safe_word -1996925065 - (341149398 - 28452500) .int 37723245 + 495950197 - .word 37723245 - 495950197 + 451460 - .word 451460 - (495950197 - 37723245) + .safe_word 37723245 - 495950197 + 451460 + .safe_word 451460 - (495950197 - 37723245) .int 37670940 + 471246474 - .word 37670940 - 471246474 + -675029989 - .word -675029989 - (471246474 - 37670940) + .safe_word 37670940 - 471246474 + -675029989 + .safe_word -675029989 - (471246474 - 37670940) .int 37618635 + 446542751 - .word 37618635 - 446542751 + -1350511438 - .word -1350511438 - (446542751 - 37618635) + .safe_word 37618635 - 446542751 + -1350511438 + .safe_word -1350511438 - (446542751 - 37618635) .int 37566330 + 421839028 - .word 37566330 - 421839028 + -2025992887 - .word -2025992887 - (421839028 - 37566330) + .safe_word 37566330 - 421839028 + -2025992887 + .safe_word -2025992887 - (421839028 - 37566330) .int 46840516 + 595146830 - .word 46840516 - 595146830 + 532721 - .word 532721 - (595146830 - 46840516) + .safe_word 46840516 - 595146830 + 532721 + .safe_word 532721 - (595146830 - 46840516) .int 46787064 + 564274106 - .word 46787064 - 564274106 + -684665089 - .word -684665089 - (564274106 - 46787064) + .safe_word 46787064 - 564274106 + -684665089 + .safe_word -684665089 - (564274106 - 46787064) .int 46733612 + 533401382 - .word 46733612 - 533401382 + -1369862899 - .word -1369862899 - (533401382 - 46733612) + .safe_word 46733612 - 533401382 + -1369862899 + .safe_word -1369862899 - (533401382 - 46733612) .int 46680160 + 502528658 - .word 46680160 - 502528658 + -2055060709 - .word -2055060709 - (502528658 - 46680160) + .safe_word 46680160 - 502528658 + -2055060709 + .safe_word -2055060709 - (502528658 - 46680160) .int 55957787 + 694343463 - .word 55957787 - 694343463 + 613982 - .word 613982 - (694343463 - 55957787) + .safe_word 55957787 - 694343463 + 613982 + .safe_word 613982 - (694343463 - 55957787) .int 55903188 + 657301738 - .word 55903188 - 657301738 + -694300189 - .word -694300189 - (657301738 - 55903188) + .safe_word 55903188 - 657301738 + -694300189 + .safe_word -694300189 - (657301738 - 55903188) .int 55848589 + 620260013 - .word 55848589 - 620260013 + -1389214360 - .word -1389214360 - (620260013 - 55848589) + .safe_word 55848589 - 620260013 + -1389214360 + .safe_word -1389214360 - (620260013 - 55848589) .int 55793990 + 583218288 - .word 55793990 - 583218288 + -2084128531 - .word -2084128531 - (583218288 - 55793990) + .safe_word 55793990 - 583218288 + -2084128531 + .safe_word -2084128531 - (583218288 - 55793990) .int 65075058 + 793540096 - .word 65075058 - 793540096 + 695243 - .word 695243 - (793540096 - 65075058) + .safe_word 65075058 - 793540096 + 695243 + .safe_word 695243 - (793540096 - 65075058) .int 65019312 + 750329370 - .word 65019312 - 750329370 + -703935289 - .word -703935289 - (750329370 - 65019312) + .safe_word 65019312 - 750329370 + -703935289 + .safe_word -703935289 - (750329370 - 65019312) .int 64963566 + 707118644 - .word 64963566 - 707118644 + -1408565821 - .word -1408565821 - (707118644 - 64963566) + .safe_word 64963566 - 707118644 + -1408565821 + .safe_word -1408565821 - (707118644 - 64963566) .int 64907820 + 663907918 - .word 64907820 - 663907918 + -2113196353 - .word -2113196353 - (663907918 - 64907820) + .safe_word 64907820 - 663907918 + -2113196353 + .safe_word -2113196353 - (663907918 - 64907820) .int 74192329 + 892736729 - .word 74192329 - 892736729 + 776504 - .word 776504 - (892736729 - 74192329) + .safe_word 74192329 - 892736729 + 776504 + .safe_word 776504 - (892736729 - 74192329) .int 74135436 + 843357002 - .word 74135436 - 843357002 + -713570389 - .word -713570389 - (843357002 - 74135436) + .safe_word 74135436 - 843357002 + -713570389 + .safe_word -713570389 - (843357002 - 74135436) .int 74078543 + 793977275 - .word 74078543 - 793977275 + -1427917282 - .word -1427917282 - (793977275 - 74078543) + .safe_word 74078543 - 793977275 + -1427917282 + .safe_word -1427917282 - (793977275 - 74078543) .int 74021650 + 744597548 - .word 74021650 - 744597548 + -2142264175 - .word -2142264175 - (744597548 - 74021650) + .safe_word 74021650 - 744597548 + -2142264175 + .safe_word -2142264175 - (744597548 - 74021650) .int 83309600 + 991933362 - .word 83309600 - 991933362 + 857765 - .word 857765 - (991933362 - 83309600) + .safe_word 83309600 - 991933362 + 857765 + .safe_word 857765 - (991933362 - 83309600) .int 83251560 + 936384634 - .word 83251560 - 936384634 + -723205489 - .word -723205489 - (936384634 - 83251560) + .safe_word 83251560 - 936384634 + -723205489 + .safe_word -723205489 - (936384634 - 83251560) .int 83193520 + 880835906 - .word 83193520 - 880835906 + -1447268743 - .word -1447268743 - (880835906 - 83193520) + .safe_word 83193520 - 880835906 + -1447268743 + .safe_word -1447268743 - (880835906 - 83193520) .int 83135480 + 825287178 - .word 83135480 - 825287178 + 2123635299 - .word 2123635299 - (825287178 - 83135480) + .safe_word 83135480 - 825287178 + 2123635299 + .safe_word 2123635299 - (825287178 - 83135480) .int 92426871 + 1091129995 - .word 92426871 - 1091129995 + 939026 - .word 939026 - (1091129995 - 92426871) + .safe_word 92426871 - 1091129995 + 939026 + .safe_word 939026 - (1091129995 - 92426871) .int 92367684 + 1029412266 - .word 92367684 - 1029412266 + -732840589 - .word -732840589 - (1029412266 - 92367684) + .safe_word 92367684 - 1029412266 + -732840589 + .safe_word -732840589 - (1029412266 - 92367684) .int 92308497 + 967694537 - .word 92308497 - 967694537 + -1466620204 - .word -1466620204 - (967694537 - 92308497) + .safe_word 92308497 - 967694537 + -1466620204 + .safe_word -1466620204 - (967694537 - 92308497) .int 92249310 + 905976808 - .word 92249310 - 905976808 + 2094567477 - .word 2094567477 - (905976808 - 92249310) + .safe_word 92249310 - 905976808 + 2094567477 + .safe_word 2094567477 - (905976808 - 92249310) .int 101544142 + 1190326628 - .word 101544142 - 1190326628 + 1020287 - .word 1020287 - (1190326628 - 101544142) + .safe_word 101544142 - 1190326628 + 1020287 + .safe_word 1020287 - (1190326628 - 101544142) .int 101483808 + 1122439898 - .word 101483808 - 1122439898 + -742475689 - .word -742475689 - (1122439898 - 101483808) + .safe_word 101483808 - 1122439898 + -742475689 + .safe_word -742475689 - (1122439898 - 101483808) .int 101423474 + 1054553168 - .word 101423474 - 1054553168 + -1485971665 - .word -1485971665 - (1054553168 - 101423474) + .safe_word 101423474 - 1054553168 + -1485971665 + .safe_word -1485971665 - (1054553168 - 101423474) .int 101363140 + 986666438 - .word 101363140 - 986666438 + 2065499655 - .word 2065499655 - (986666438 - 101363140) + .safe_word 101363140 - 986666438 + 2065499655 + .safe_word 2065499655 - (986666438 - 101363140) .int 110661413 + 1289523261 - .word 110661413 - 1289523261 + 1101548 - .word 1101548 - (1289523261 - 110661413) + .safe_word 110661413 - 1289523261 + 1101548 + .safe_word 1101548 - (1289523261 - 110661413) .int 110599932 + 1215467530 - .word 110599932 - 1215467530 + -752110789 - .word -752110789 - (1215467530 - 110599932) - .int 110538451 + 1141411799 - .word 110538451 - 1141411799 + -1505323126 - .word -1505323126 - (1141411799 - 110538451) + .safe_word 110599932 - 1215467530 + -752110789 + .safe_word -752110789 - (1215467530 - 110599932) + .safe_word 110538451 + 1141411799 + .safe_word 110538451 - 1141411799 + -1505323126 + .safe_word -1505323126 - (1141411799 - 110538451) .int 110476970 + 1067356068 - .word 110476970 - 1067356068 + 2036431833 - .word 2036431833 - (1067356068 - 110476970) + .safe_word 110476970 - 1067356068 + 2036431833 + .safe_word 2036431833 - (1067356068 - 110476970) .int 119778684 + 1388719894 - .word 119778684 - 1388719894 + 1182809 - .word 1182809 - (1388719894 - 119778684) + .safe_word 119778684 - 1388719894 + 1182809 + .safe_word 1182809 - (1388719894 - 119778684) .int 119716056 + 1308495162 - .word 119716056 - 1308495162 + -761745889 - .word -761745889 - (1308495162 - 119716056) + .safe_word 119716056 - 1308495162 + -761745889 + .safe_word -761745889 - (1308495162 - 119716056) .int 119653428 + 1228270430 - .word 119653428 - 1228270430 + -1524674587 - .word -1524674587 - (1228270430 - 119653428) + .safe_word 119653428 - 1228270430 + -1524674587 + .safe_word -1524674587 - (1228270430 - 119653428) .int 119590800 + 1148045698 - .word 119590800 - 1148045698 + 2007364011 - .word 2007364011 - (1148045698 - 119590800) + .safe_word 119590800 - 1148045698 + 2007364011 + .safe_word 2007364011 - (1148045698 - 119590800) .int 128895955 + 1487916527 - .word 128895955 - 1487916527 + 1264070 - .word 1264070 - (1487916527 - 128895955) + .safe_word 128895955 - 1487916527 + 1264070 + .safe_word 1264070 - (1487916527 - 128895955) .int 128832180 + 1401522794 - .word 128832180 - 1401522794 + -771380989 - .word -771380989 - (1401522794 - 128832180) + .safe_word 128832180 - 1401522794 + -771380989 + .safe_word -771380989 - (1401522794 - 128832180) .int 128768405 + 1315129061 - .word 128768405 - 1315129061 + -1544026048 - .word -1544026048 - (1315129061 - 128768405) + .safe_word 128768405 - 1315129061 + -1544026048 + .safe_word -1544026048 - (1315129061 - 128768405) .int 128704630 + 1228735328 - .word 128704630 - 1228735328 + 1978296189 - .word 1978296189 - (1228735328 - 128704630) + .safe_word 128704630 - 1228735328 + 1978296189 + .safe_word 1978296189 - (1228735328 - 128704630) .int 138013226 + 1587113160 - .word 138013226 - 1587113160 + 1345331 - .word 1345331 - (1587113160 - 138013226) + .safe_word 138013226 - 1587113160 + 1345331 + .safe_word 1345331 - (1587113160 - 138013226) .int 137948304 + 1494550426 - .word 137948304 - 1494550426 + -781016089 - .word -781016089 - (1494550426 - 137948304) + .safe_word 137948304 - 1494550426 + -781016089 + .safe_word -781016089 - (1494550426 - 137948304) .int 137883382 + 1401987692 - .word 137883382 - 1401987692 + -1563377509 - .word -1563377509 - (1401987692 - 137883382) + .safe_word 137883382 - 1401987692 + -1563377509 + .safe_word -1563377509 - (1401987692 - 137883382) .int 137818460 + 1309424958 - .word 137818460 - 1309424958 + 1949228367 - .word 1949228367 - (1309424958 - 137818460) + .safe_word 137818460 - 1309424958 + 1949228367 + .safe_word 1949228367 - (1309424958 - 137818460) .int 147130497 + 1686309793 - .word 147130497 - 1686309793 + 1426592 - .word 1426592 - (1686309793 - 147130497) + .safe_word 147130497 - 1686309793 + 1426592 + .safe_word 1426592 - (1686309793 - 147130497) .int 147064428 + 1587578058 - .word 147064428 - 1587578058 + -790651189 - .word -790651189 - (1587578058 - 147064428) + .safe_word 147064428 - 1587578058 + -790651189 + .safe_word -790651189 - (1587578058 - 147064428) .int 146998359 + 1488846323 - .word 146998359 - 1488846323 + -1582728970 - .word -1582728970 - (1488846323 - 146998359) + .safe_word 146998359 - 1488846323 + -1582728970 + .safe_word -1582728970 - (1488846323 - 146998359) .int 146932290 + 1390114588 - .word 146932290 - 1390114588 + 1920160545 - .word 1920160545 - (1390114588 - 146932290) + .safe_word 146932290 - 1390114588 + 1920160545 + .safe_word 1920160545 - (1390114588 - 146932290) .int 156247768 + 1785506426 - .word 156247768 - 1785506426 + 1507853 - .word 1507853 - (1785506426 - 156247768) + .safe_word 156247768 - 1785506426 + 1507853 + .safe_word 1507853 - (1785506426 - 156247768) .int 156180552 + 1680605690 - .word 156180552 - 1680605690 + -800286289 - .word -800286289 - (1680605690 - 156180552) + .safe_word 156180552 - 1680605690 + -800286289 + .safe_word -800286289 - (1680605690 - 156180552) .int 156113336 + 1575704954 - .word 156113336 - 1575704954 + -1602080431 - .word -1602080431 - (1575704954 - 156113336) + .safe_word 156113336 - 1575704954 + -1602080431 + .safe_word -1602080431 - (1575704954 - 156113336) .int 156046120 + 1470804218 - .word 156046120 - 1470804218 + 1891092723 - .word 1891092723 - (1470804218 - 156046120) + .safe_word 156046120 - 1470804218 + 1891092723 + .safe_word 1891092723 - (1470804218 - 156046120) .int 165365039 + 1884703059 - .word 165365039 - 1884703059 + 1589114 - .word 1589114 - (1884703059 - 165365039) + .safe_word 165365039 - 1884703059 + 1589114 + .safe_word 1589114 - (1884703059 - 165365039) .int 165296676 + 1773633322 - .word 165296676 - 1773633322 + -809921389 - .word -809921389 - (1773633322 - 165296676) + .safe_word 165296676 - 1773633322 + -809921389 + .safe_word -809921389 - (1773633322 - 165296676) .int 165228313 + 1662563585 - .word 165228313 - 1662563585 + -1621431892 - .word -1621431892 - (1662563585 - 165228313) + .safe_word 165228313 - 1662563585 + -1621431892 + .safe_word -1621431892 - (1662563585 - 165228313) .int 165159950 + 1551493848 - .word 165159950 - 1551493848 + 1862024901 - .word 1862024901 - (1551493848 - 165159950) + .safe_word 165159950 - 1551493848 + 1862024901 + .safe_word 1862024901 - (1551493848 - 165159950) .int 174482310 + 1983899692 - .word 174482310 - 1983899692 + 1670375 - .word 1670375 - (1983899692 - 174482310) + .safe_word 174482310 - 1983899692 + 1670375 + .safe_word 1670375 - (1983899692 - 174482310) .int 174412800 + 1866660954 - .word 174412800 - 1866660954 + -819556489 - .word -819556489 - (1866660954 - 174412800) + .safe_word 174412800 - 1866660954 + -819556489 + .safe_word -819556489 - (1866660954 - 174412800) .int 174343290 + 1749422216 - .word 174343290 - 1749422216 + -1640783353 - .word -1640783353 - (1749422216 - 174343290) + .safe_word 174343290 - 1749422216 + -1640783353 + .safe_word -1640783353 - (1749422216 - 174343290) .int 174273780 + 1632183478 - .word 174273780 - 1632183478 + 1832957079 - .word 1832957079 - (1632183478 - 174273780) + .safe_word 174273780 - 1632183478 + 1832957079 + .safe_word 1832957079 - (1632183478 - 174273780) .int 183599581 + 2083096325 - .word 183599581 - 2083096325 + 1751636 - .word 1751636 - (2083096325 - 183599581) + .safe_word 183599581 - 2083096325 + 1751636 + .safe_word 1751636 - (2083096325 - 183599581) .int 183528924 + 1959688586 - .word 183528924 - 1959688586 + -829191589 - .word -829191589 - (1959688586 - 183528924) + .safe_word 183528924 - 1959688586 + -829191589 + .safe_word -829191589 - (1959688586 - 183528924) .int 183458267 + 1836280847 - .word 183458267 - 1836280847 + -1660134814 - .word -1660134814 - (1836280847 - 183458267) + .safe_word 183458267 - 1836280847 + -1660134814 + .safe_word -1660134814 - (1836280847 - 183458267) .int 183387610 + 1712873108 - .word 183387610 - 1712873108 + 1803889257 - .word 1803889257 - (1712873108 - 183387610) + .safe_word 183387610 - 1712873108 + 1803889257 + .safe_word 1803889257 - (1712873108 - 183387610) .int 192716852 + -2112674338 - .word 192716852 - -2112674338 + 1832897 - .word 1832897 - (-2112674338 - 192716852) + .safe_word 192716852 - -2112674338 + 1832897 + .safe_word 1832897 - (-2112674338 - 192716852) .int 192645048 + 2052716218 - .word 192645048 - 2052716218 + -838826689 - .word -838826689 - (2052716218 - 192645048) + .safe_word 192645048 - 2052716218 + -838826689 + .safe_word -838826689 - (2052716218 - 192645048) .int 192573244 + 1923139478 - .word 192573244 - 1923139478 + -1679486275 - .word -1679486275 - (1923139478 - 192573244) + .safe_word 192573244 - 1923139478 + -1679486275 + .safe_word -1679486275 - (1923139478 - 192573244) .int 192501440 + 1793562738 - .word 192501440 - 1793562738 + 1774821435 - .word 1774821435 - (1793562738 - 192501440) + .safe_word 192501440 - 1793562738 + 1774821435 + .safe_word 1774821435 - (1793562738 - 192501440) .int 201834123 + -2013477705 - .word 201834123 - -2013477705 + 1914158 - .word 1914158 - (-2013477705 - 201834123) + .safe_word 201834123 - -2013477705 + 1914158 + .safe_word 1914158 - (-2013477705 - 201834123) .int 201761172 + 2145743850 - .word 201761172 - 2145743850 + -848461789 - .word -848461789 - (2145743850 - 201761172) + .safe_word 201761172 - 2145743850 + -848461789 + .safe_word -848461789 - (2145743850 - 201761172) .int 201688221 + 2009998109 - .word 201688221 - 2009998109 + -1698837736 - .word -1698837736 - (2009998109 - 201688221) + .safe_word 201688221 - 2009998109 + -1698837736 + .safe_word -1698837736 - (2009998109 - 201688221) .int 201615270 + 1874252368 - .word 201615270 - 1874252368 + 1745753613 - .word 1745753613 - (1874252368 - 201615270) + .safe_word 201615270 - 1874252368 + 1745753613 + .safe_word 1745753613 - (1874252368 - 201615270) .int 210951394 + -1914281072 - .word 210951394 - -1914281072 + 1995419 - .word 1995419 - (-1914281072 - 210951394) + .safe_word 210951394 - -1914281072 + 1995419 + .safe_word 1995419 - (-1914281072 - 210951394) .int 210877296 + -2056195814 - .word 210877296 - -2056195814 + -858096889 - .word -858096889 - (-2056195814 - 210877296) + .safe_word 210877296 - -2056195814 + -858096889 + .safe_word -858096889 - (-2056195814 - 210877296) .int 210803198 + 2096856740 - .word 210803198 - 2096856740 + -1718189197 - .word -1718189197 - (2096856740 - 210803198) + .safe_word 210803198 - 2096856740 + -1718189197 + .safe_word -1718189197 - (2096856740 - 210803198) .int 210729100 + 1954941998 - .word 210729100 - 1954941998 + 1716685791 - .word 1716685791 - (1954941998 - 210729100) + .safe_word 210729100 - 1954941998 + 1716685791 + .safe_word 1716685791 - (1954941998 - 210729100) .int 220068665 + -1815084439 - .word 220068665 - -1815084439 + 2076680 - .word 2076680 - (-1815084439 - 220068665) + .safe_word 220068665 - -1815084439 + 2076680 + .safe_word 2076680 - (-1815084439 - 220068665) .int 219993420 + -1963168182 - .word 219993420 - -1963168182 + -867731989 - .word -867731989 - (-1963168182 - 219993420) + .safe_word 219993420 - -1963168182 + -867731989 + .safe_word -867731989 - (-1963168182 - 219993420) .int 219918175 + -2111251925 - .word 219918175 - -2111251925 + -1737540658 - .word -1737540658 - (-2111251925 - 219918175) + .safe_word 219918175 - -2111251925 + -1737540658 + .safe_word -1737540658 - (-2111251925 - 219918175) .int 219842930 + 2035631628 - .word 219842930 - 2035631628 + 1687617969 - .word 1687617969 - (2035631628 - 219842930) + .safe_word 219842930 - 2035631628 + 1687617969 + .safe_word 1687617969 - (2035631628 - 219842930) .int 229185936 + -1715887806 - .word 229185936 - -1715887806 + 2157941 - .word 2157941 - (-1715887806 - 229185936) + .safe_word 229185936 - -1715887806 + 2157941 + .safe_word 2157941 - (-1715887806 - 229185936) .int 229109544 + -1870140550 - .word 229109544 - -1870140550 + -877367089 - .word -877367089 - (-1870140550 - 229109544) + .safe_word 229109544 - -1870140550 + -877367089 + .safe_word -877367089 - (-1870140550 - 229109544) .int 229033152 + -2024393294 - .word 229033152 - -2024393294 + -1756892119 - .word -1756892119 - (-2024393294 - 229033152) + .safe_word 229033152 - -2024393294 + -1756892119 + .safe_word -1756892119 - (-2024393294 - 229033152) .int 228956760 + 2116321258 - .word 228956760 - 2116321258 + 1658550147 - .word 1658550147 - (2116321258 - 228956760) + .safe_word 228956760 - 2116321258 + 1658550147 + .safe_word 1658550147 - (2116321258 - 228956760) .int 238303207 + -1616691173 - .word 238303207 - -1616691173 + 2239202 - .word 2239202 - (-1616691173 - 238303207) + .safe_word 238303207 - -1616691173 + 2239202 + .safe_word 2239202 - (-1616691173 - 238303207) .int 238225668 + -1777112918 - .word 238225668 - -1777112918 + -887002189 - .word -887002189 - (-1777112918 - 238225668) + .safe_word 238225668 - -1777112918 + -887002189 + .safe_word -887002189 - (-1777112918 - 238225668) .int 238148129 + -1937534663 - .word 238148129 - -1937534663 + -1776243580 - .word -1776243580 - (-1937534663 - 238148129) + .safe_word 238148129 - -1937534663 + -1776243580 + .safe_word -1776243580 - (-1937534663 - 238148129) .int 238070590 + -2097956408 - .word 238070590 - -2097956408 + 1629482325 - .word 1629482325 - (-2097956408 - 238070590) + .safe_word 238070590 - -2097956408 + 1629482325 + .safe_word 1629482325 - (-2097956408 - 238070590) .int 247420478 + -1517494540 - .word 247420478 - -1517494540 + 2320463 - .word 2320463 - (-1517494540 - 247420478) + .safe_word 247420478 - -1517494540 + 2320463 + .safe_word 2320463 - (-1517494540 - 247420478) .int 247341792 + -1684085286 - .word 247341792 - -1684085286 + -896637289 - .word -896637289 - (-1684085286 - 247341792) + .safe_word 247341792 - -1684085286 + -896637289 + .safe_word -896637289 - (-1684085286 - 247341792) .int 247263106 + -1850676032 - .word 247263106 - -1850676032 + -1795595041 - .word -1795595041 - (-1850676032 - 247263106) + .safe_word 247263106 - -1850676032 + -1795595041 + .safe_word -1795595041 - (-1850676032 - 247263106) .int 247184420 + -2017266778 - .word 247184420 - -2017266778 + 1600414503 - .word 1600414503 - (-2017266778 - 247184420) + .safe_word 247184420 - -2017266778 + 1600414503 + .safe_word 1600414503 - (-2017266778 - 247184420) .int 256537749 + -1418297907 - .word 256537749 - -1418297907 + 2401724 - .word 2401724 - (-1418297907 - 256537749) + .safe_word 256537749 - -1418297907 + 2401724 + .safe_word 2401724 - (-1418297907 - 256537749) .int 256457916 + -1591057654 - .word 256457916 - -1591057654 + -906272389 - .word -906272389 - (-1591057654 - 256457916) + .safe_word 256457916 - -1591057654 + -906272389 + .safe_word -906272389 - (-1591057654 - 256457916) .int 256378083 + -1763817401 - .word 256378083 - -1763817401 + -1814946502 - .word -1814946502 - (-1763817401 - 256378083) + .safe_word 256378083 - -1763817401 + -1814946502 + .safe_word -1814946502 - (-1763817401 - 256378083) .int 256298250 + -1936577148 - .word 256298250 - -1936577148 + 1571346681 - .word 1571346681 - (-1936577148 - 256298250) + .safe_word 256298250 - -1936577148 + 1571346681 + .safe_word 1571346681 - (-1936577148 - 256298250) .int 265655020 + -1319101274 - .word 265655020 - -1319101274 + 2482985 - .word 2482985 - (-1319101274 - 265655020) + .safe_word 265655020 - -1319101274 + 2482985 + .safe_word 2482985 - (-1319101274 - 265655020) .int 265574040 + -1498030022 - .word 265574040 - -1498030022 + -915907489 - .word -915907489 - (-1498030022 - 265574040) + .safe_word 265574040 - -1498030022 + -915907489 + .safe_word -915907489 - (-1498030022 - 265574040) .int 265493060 + -1676958770 - .word 265493060 - -1676958770 + -1834297963 - .word -1834297963 - (-1676958770 - 265493060) + .safe_word 265493060 - -1676958770 + -1834297963 + .safe_word -1834297963 - (-1676958770 - 265493060) .int 265412080 + -1855887518 - .word 265412080 - -1855887518 + 1542278859 - .word 1542278859 - (-1855887518 - 265412080) + .safe_word 265412080 - -1855887518 + 1542278859 + .safe_word 1542278859 - (-1855887518 - 265412080) .int 274772291 + -1219904641 - .word 274772291 - -1219904641 + 2564246 - .word 2564246 - (-1219904641 - 274772291) + .safe_word 274772291 - -1219904641 + 2564246 + .safe_word 2564246 - (-1219904641 - 274772291) .int 274690164 + -1405002390 - .word 274690164 - -1405002390 + -925542589 - .word -925542589 - (-1405002390 - 274690164) + .safe_word 274690164 - -1405002390 + -925542589 + .safe_word -925542589 - (-1405002390 - 274690164) .int 274608037 + -1590100139 - .word 274608037 - -1590100139 + -1853649424 - .word -1853649424 - (-1590100139 - 274608037) + .safe_word 274608037 - -1590100139 + -1853649424 + .safe_word -1853649424 - (-1590100139 - 274608037) .int 274525910 + -1775197888 - .word 274525910 - -1775197888 + 1513211037 - .word 1513211037 - (-1775197888 - 274525910) + .safe_word 274525910 - -1775197888 + 1513211037 + .safe_word 1513211037 - (-1775197888 - 274525910) .int 283889562 + -1120708008 - .word 283889562 - -1120708008 + 2645507 - .word 2645507 - (-1120708008 - 283889562) + .safe_word 283889562 - -1120708008 + 2645507 + .safe_word 2645507 - (-1120708008 - 283889562) .int 283806288 + -1311974758 - .word 283806288 - -1311974758 + -935177689 - .word -935177689 - (-1311974758 - 283806288) + .safe_word 283806288 - -1311974758 + -935177689 + .safe_word -935177689 - (-1311974758 - 283806288) .int 283723014 + -1503241508 - .word 283723014 - -1503241508 + -1873000885 - .word -1873000885 - (-1503241508 - 283723014) + .safe_word 283723014 - -1503241508 + -1873000885 + .safe_word -1873000885 - (-1503241508 - 283723014) .int 283639740 + -1694508258 - .word 283639740 - -1694508258 + 1484143215 - .word 1484143215 - (-1694508258 - 283639740) + .safe_word 283639740 - -1694508258 + 1484143215 + .safe_word 1484143215 - (-1694508258 - 283639740) .word label_1, label_2, label_3 .word label_1 - 37 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9ca0760acca..56b7f9693a0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2016-06-15 Nick Clifton + + * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer + constants to match expected behaviour. + (nds32_parse_opcode): Likewise. Also for whitespace. + 2016-06-15 Andrew Burgess * arc-opc.c (extract_rhv1): Extract value from insn. diff --git a/opcodes/nds32-dis.c b/opcodes/nds32-dis.c index 665634293f0..e88e3bffa19 100644 --- a/opcodes/nds32-dis.c +++ b/opcodes/nds32-dis.c @@ -155,7 +155,7 @@ nds32_parse_audio_ext (const field_t *pfd, else int_value = __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; - if (int_value < 0) + if (int_value < 10) func (stream, "#%d", int_value); else func (stream, "#0x%x", int_value); @@ -269,7 +269,7 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, else if (strstr (opc->instruction, "tito")) func (stream, "%s", opc->opcode); else - func (stream, "%s ", opc->opcode); + func (stream, "%s\t", opc->opcode); } while (*pstr_src) @@ -280,7 +280,7 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, case '=': case '&': pstr_src++; - /* compare with operand_fields[].name. */ + /* Compare with operand_fields[].name. */ pstr_tmp = &tmp_string[0]; while (*pstr_src) { @@ -304,7 +304,7 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, pfd++; } - /* for insn-16. */ + /* For insn-16. */ if (parse_mode & NDS32_PARSE_INSN16) { if (pfd->hw_res == HW_GPR) @@ -373,13 +373,18 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, } else if (pfd->hw_res == HW_INT) { - if (int_value < 0) + if (int_value < 10) func (stream, "#%d", int_value); else func (stream, "#0x%x", int_value); } - else /* if(pfd->hw_res == HW_UINT). */ - func (stream, "#0x%x", int_value); + else /* if (pfd->hw_res == HW_UINT). */ + { + if (int_value < 10) + func (stream, "#%u", int_value); + else + func (stream, "#0x%x", int_value); + } } } @@ -491,14 +496,17 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, } else if (pfd->hw_res == HW_INT) { - if (int_value < 0) + if (int_value < 10) func (stream, "#%d", int_value); else func (stream, "#0x%x", int_value); } - else /* if(pfd->hw_res == HW_UINT). */ + else /* if (pfd->hw_res == HW_UINT). */ { - func (stream, "#0x%x", int_value); + if (int_value < 10) + func (stream, "#%u", int_value); + else + func (stream, "#0x%x", int_value); } } break; @@ -508,13 +516,34 @@ nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, pstr_src++; break; + case ',': + func (stream, ", "); + pstr_src++; + break; + + case '+': + func (stream, " + "); + pstr_src++; + break; + + case '<': + if (pstr_src[1] == '<') + { + func (stream, " << "); + pstr_src += 2; + } + else + { + func (stream, " <"); + pstr_src++; + } + break; + default: func (stream, "%c", *pstr_src++); break; - } /* switch (*pstr_src). */ - - } /* while (*pstr_src). */ - return; + } + } } /* Filter instructions with some bits must be fixed. */