From: Andreas Krebbel Date: Fri, 1 Aug 2003 15:41:59 +0000 (+0000) Subject: s390.c (s390_select_ccmode): Do not attempt to use CCL, CCL1, or CCL2 modes with... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ef093a8252e0048e18d40e5748d04486217500e;p=gcc.git s390.c (s390_select_ccmode): Do not attempt to use CCL, CCL1, or CCL2 modes with floating point operations. 2003-08-01 Andreas Krebbel * config/s390/s390.c (s390_select_ccmode): Do not attempt to use CCL, CCL1, or CCL2 modes with floating point operations. * config/s390/s390.md ("*addsf3_cc", "*addsf3_cconly", "*adddf3_cc", "*adddf3_cconly", "*subsf3_cc", "*subsf3_cconly", "*subdf3_cc", "*subdf3_cconly"): New insns. ("*negabssi2", "*negabsdi2", "*negabsdf2", "*negabssf2"): Likewise. From-SVN: r70052 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 625eb041342..cdac9b2f37d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2003-08-01 Andreas Krebbel + + * config/s390/s390.c (s390_select_ccmode): Do not attempt to use CCL, + CCL1, or CCL2 modes with floating point operations. + + * config/s390/s390.md ("*addsf3_cc", "*addsf3_cconly", "*adddf3_cc", + "*adddf3_cconly", "*subsf3_cc", "*subsf3_cconly", "*subdf3_cc", + "*subdf3_cconly"): New insns. + ("*negabssi2", "*negabsdi2", "*negabsdf2", "*negabssf2"): Likewise. + 2003-08-01 Neil Booth * Makefile.in: Refine dependencies. diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 9d47de16ec2..5684a6ac9d9 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -377,8 +377,9 @@ s390_select_ccmode (code, op0, op1) if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K')) return CCAPmode; - if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS - || GET_CODE (op1) == NEG) + if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS + || GET_CODE (op1) == NEG) + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) return CCLmode; if (GET_CODE (op0) == AND) @@ -432,7 +433,8 @@ s390_select_ccmode (code, op0, op1) case LTU: case GEU: - if (GET_CODE (op0) == PLUS) + if (GET_CODE (op0) == PLUS + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) return CCL1mode; if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) @@ -442,7 +444,8 @@ s390_select_ccmode (code, op0, op1) case LEU: case GTU: - if (GET_CODE (op0) == MINUS) + if (GET_CODE (op0) == MINUS + && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) return CCL2mode; if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e1a25cc8ef5..c7f1312b2d2 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -3451,6 +3451,33 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimpd,fsimpd")]) +(define_insn "*adddf3_cc" + [(set (reg 33) + (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (set (match_operand:DF 0 "register_operand" "=f,f") + (plus:DF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + adbr\\t%0,%2 + adb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*adddf3_cconly" + [(set (reg 33) + (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (clobber (match_scratch:DF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + adbr\\t%0,%2 + adb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + (define_insn "*adddf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") @@ -3488,6 +3515,33 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimps,fsimps")]) +(define_insn "*addsf3_cc" + [(set (reg 33) + (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (set (match_operand:SF 0 "register_operand" "=f,f") + (plus:SF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + aebr\\t%0,%2 + aeb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*addsf3_cconly" + [(set (reg 33) + (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (clobber (match_scratch:SF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + aebr\\t%0,%2 + aeb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + (define_insn "*addsf3" [(set (match_operand:SF 0 "register_operand" "=f,f") (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") @@ -3752,6 +3806,33 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimpd,fsimpd")]) +(define_insn "*subdf3_cc" + [(set (reg 33) + (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (set (match_operand:DF 0 "register_operand" "=f,f") + (plus:DF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sdbr\\t%0,%2 + sdb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*subdf3_cconly" + [(set (reg 33) + (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (clobber (match_scratch:DF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sdbr\\t%0,%2 + sdb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + (define_insn "*subdf3_ibm" [(set (match_operand:DF 0 "register_operand" "=f,f") (minus:DF (match_operand:DF 1 "register_operand" "0,0") @@ -3789,6 +3870,33 @@ [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimps,fsimps")]) +(define_insn "*subsf3_cc" + [(set (reg 33) + (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (set (match_operand:SF 0 "register_operand" "=f,f") + (minus:SF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sebr\\t%0,%2 + seb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*subsf3_cconly" + [(set (reg 33) + (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (clobber (match_scratch:SF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sebr\\t%0,%2 + seb\\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + (define_insn "*subsf3_ibm" [(set (match_operand:SF 0 "register_operand" "=f,f") (minus:SF (match_operand:SF 1 "register_operand" "0,0") @@ -5332,6 +5440,52 @@ [(set_attr "op_type" "RR") (set_attr "type" "fsimps")]) +;; +;;- Negated absolute value instructions +;; + +; +; Integer +; + +(define_insn "*negabssi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) + (clobber (reg:CC 33))] + "" + "lnr\\t%0,%1" + [(set_attr "op_type" "RR")]) + +(define_insn "*negabsdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "lngr\\t%0,%1" + [(set_attr "op_type" "RRE")]) + +; +; Floating point +; + +(define_insn "*negabssf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) + (clobber (reg:CC 33))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "lnebr\\t%0,%1" + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimps")]) + +(define_insn "*negabsdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (reg:CC 33))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "lndbr\\t%0,%1" + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimpd")]) + ;; ;;- Square root instructions. ;;