From: Gabor Dozsa <gabor.dozsa@arm.com>
Date: Tue, 6 Dec 2016 17:10:36 +0000 (+0000)
Subject: arm, config: Add missing IOCache in bL config
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3ef797623abaeb93049d59c8e90ba57f2ee9c7e1;p=gem5.git

arm, config: Add missing IOCache in bL config

This patch adds an IOCache to the example bigLITTLE
configuration. An IOCache is required for correct DMA
transfers when we have caches in the system.

Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 6734aaf5c..7d3f383f3 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -174,7 +174,7 @@ class AtomicCluster(CpuCluster):
 class SimpleSystem(LinuxArmSystem):
     cache_line_size = 64
 
-    def __init__(self, **kwargs):
+    def __init__(self, caches, mem_size, **kwargs):
         super(SimpleSystem, self).__init__(**kwargs)
 
         self.voltage_domain = VoltageDomain(voltage="1.0V")
@@ -196,8 +196,16 @@ class SimpleSystem(LinuxArmSystem):
         # CPUs->PIO
         self.iobridge = Bridge(delay='50ns')
         # Device DMA -> MEM
-        self.dmabridge = Bridge(delay='50ns',
-                                ranges=self.realview._mem_regions)
+        mem_range = self.realview._mem_regions[0]
+        mem_range_size = long(mem_range[1]) - long(mem_range[0])
+        assert mem_range_size >= long(Addr(mem_size))
+        self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
+        self._caches = caches
+        if self._caches:
+            self.iocache = IOCache(addr_ranges=[self._mem_range])
+        else:
+            self.dmabridge = Bridge(delay='50ns',
+                                    ranges=[self._mem_range])
 
         self._pci_devices = 0
         self._clusters = []
@@ -212,8 +220,12 @@ class SimpleSystem(LinuxArmSystem):
         self.iobridge.master = self.iobus.slave
         self.iobridge.slave = self.membus.master
 
-        self.dmabridge.master = self.membus.slave
-        self.dmabridge.slave = self.iobus.master
+        if self._caches:
+            self.iocache.mem_side = self.membus.slave
+            self.iocache.cpu_side = self.iobus.master
+        else:
+            self.dmabridge.master = self.membus.slave
+            self.dmabridge.slave = self.iobus.master
 
         self.gic_cpu_addr = self.realview.gic.cpu_addr
         self.realview.attachOnChipIO(self.membus, self.iobridge)
diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py
index d1b1ee7ab..75cb44184 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -79,14 +79,13 @@ class LittleCluster(devices.CpuCluster):
                                          cpu_voltage, *cpu_config)
 
 
-def createSystem(kernel, bootscript, disks=[]):
-    sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
+def createSystem(caches, kernel, bootscript, disks=[]):
+    sys = devices.SimpleSystem(caches, default_mem_size,
+                               kernel=SysPaths.binary(kernel),
                                readfile=bootscript,
                                machine_type="DTOnly")
 
-    mem_region = sys.realview._mem_regions[0]
-    sys.mem_ctrls = SimpleMemory(
-        range=AddrRange(start=mem_region[0], size=default_mem_size))
+    sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
     sys.mem_ctrls.port = sys.membus.master
 
     sys.connect()
@@ -159,8 +158,11 @@ def main():
 
     root = Root(full_system=True)
 
-    disks = default_disk if len(options.disk) == 0 else options.disk
-    system = createSystem(options.kernel, options.bootscript, disks=disks)
+    disks = [default_disk] if len(options.disk) == 0 else options.disk
+    system = createSystem(options.caches,
+                          options.kernel,
+                          options.bootscript,
+                          disks=disks)
 
     root.system = system
     system.boot_osflags = " ".join(kernel_cmd)