From: Florent Kermarrec Date: Thu, 9 May 2019 10:13:15 +0000 (+0200) Subject: boards/targets: declare ethmac interrupt with new add_interrupt method X-Git-Tag: 24jan2021_ls180~1228 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f09af6d6e7432e8592c30178ad974acd8f07ed5;p=litex.git boards/targets: declare ethmac interrupt with new add_interrupt method The previous way to define interrupt is still valid, but using add_interrupt method will ease maintenance --- diff --git a/litex/boards/targets/ac701.py b/litex/boards/targets/ac701.py index 0933866e..a10885d1 100755 --- a/litex/boards/targets/ac701.py +++ b/litex/boards/targets/ac701.py @@ -76,11 +76,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -133,6 +128,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 98cc0adc..683b3024 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -80,11 +80,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -99,6 +94,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 1b9e1d6c..d529e0e3 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -71,11 +71,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -90,6 +85,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 954fe954..93b435a9 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -71,11 +71,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -90,6 +85,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 9067ceed..5105a399 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -109,11 +109,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -129,6 +124,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.cd_eth_rx.clk.attr.add("keep") self.ethphy.cd_eth_tx.clk.attr.add("keep") diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 7125d1a6..e82f1990 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -75,11 +75,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -94,6 +89,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 3c5f02c9..f7832973 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -32,11 +32,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -51,6 +46,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index ec7a572f..757b9e28 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -107,11 +107,6 @@ class EthernetSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(BaseSoC.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -127,6 +122,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")