From: Andrew Waterman Date: Tue, 2 Nov 2010 23:00:37 +0000 (-0700) Subject: [xcc, sim, pk] link register is now x1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f144b12ed35f7fee4c7faf937e144807acb1e2b;p=riscv-isa-sim.git [xcc, sim, pk] link register is now x1 --- diff --git a/riscv/insns/jal.h b/riscv/insns/jal.h index 7995b15..7a70307 100644 --- a/riscv/insns/jal.h +++ b/riscv/insns/jal.h @@ -1,2 +1,2 @@ -R[31] = npc; +R[1] = npc; npc = JUMP_TARGET; diff --git a/riscv/sim.cc b/riscv/sim.cc index ca10e09..8b04aa2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -225,6 +225,9 @@ reg_t sim_t::get_mem(const std::vector& args) throw trap_illegal_instruction; reg_t addr = strtol(args[0].c_str(),NULL,16), val; + if(addr == LONG_MAX) + addr = strtoul(args[0].c_str(),NULL,16); + mmu_t mmu(mem,memsz); switch(addr % 8) { @@ -257,6 +260,8 @@ void sim_t::interactive_until(const std::string& cmd, const std::vector args2; args2 = std::vector(args.begin()+1,args.end()-1);