From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 16:55:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f14a745757051ce2cb6af9223e24b5ee4f4cfe4;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 06c8f0634..3766c12a8 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -23,7 +23,6 @@ from existing SVP64 instructions and have been moved to [[discussion]]
 
 Notes:
 
-* Some of these actually could be added to a scalar ISA as bitmanipulation instructions.  These are separated out into their own section.
 * Instructions suited to 3D GPU workloads (dotproduct, crossproduct, normalise) are out of scope: this document is for more general-purpose instructions that underpin and are critical to general-purpose Vector workloads (including GPU and VPU)
 * Instructions related to the adaptation of CRs for use as predicate masks are covered separately, by crweird operations.  See [[sv/cr_int_predication]].