From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 19:47:55 +0000 (+0200)
Subject: revert fhdl/verilog: avoid reg initialization in printheader when reset is not an... 
X-Git-Tag: 24jan2021_ls180~2099^2~104
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f15699964e82054b4261a5100ce4fbce8a5e0dc;p=litex.git

revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 4cc657b3..5d5f5896 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns):
         if sig in wires:
             r += "wire " + _printsig(ns, sig) + ";\n"
         else:
-            if isinstance(sig.reset, int):
-                resetexpr = " = " + _printexpr(ns, sig.reset)[0]
-            else:
-                resetexpr = ""
-            r += "reg " + _printsig(ns, sig) + resetexpr + ";\n"
+            r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
     r += "\n"
     return r