From: Michael Nolan Date: Wed, 13 May 2020 18:02:13 +0000 (-0400) Subject: Fix bug with ROTL32 helper X-Git-Tag: div_pipeline~1259 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f1fbb87e0073935f3f29d4fc4e55be13121526b;p=soc.git Fix bug with ROTL32 helper Turns out it's supposed to duplicate the lower 32 bits to the high 32 bits, and do a 64 bit rotate --- diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py index ef28c7ca..e8fd6cb7 100644 --- a/src/soc/decoder/helpers.py +++ b/src/soc/decoder/helpers.py @@ -40,7 +40,9 @@ def ROTL64(value, bits): def ROTL32(value, bits): - return rotl(value, bits, 32) + if isinstance(value, SelectableInt): + value = SelectableInt(value.value, 64) + return rotl(value | (value << 32), bits, 64) def MASK(x, y): diff --git a/src/soc/decoder/isa/fixedshift.patch b/src/soc/decoder/isa/fixedshift.patch index 8485cd8c..42fc2ac6 100644 --- a/src/soc/decoder/isa/fixedshift.patch +++ b/src/soc/decoder/isa/fixedshift.patch @@ -1,62 +1,55 @@ ---- fixedshift.py.orig 2020-05-09 09:56:10.393656481 -0400 -+++ fixedshift.py 2020-05-10 18:51:24.725396454 -0400 -@@ -12,48 +12,48 @@ - @inject() +--- fixedshift.py.orig 2020-05-11 10:20:55.781417649 -0400 ++++ fixedshift.py 2020-05-13 14:02:01.147691354 -0400 +@@ -13,7 +13,7 @@ def op_rlwinm(self, RS): n = SH -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m return (RA,) - @inject() +@@ -21,7 +21,7 @@ def op_rlwinm_(self, RS): n = SH -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m return (RA,) - @inject() +@@ -29,7 +29,7 @@ def op_rlwnm(self, RB, RS): n = RB[59:64] -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m return (RA,) - @inject() +@@ -37,7 +37,7 @@ def op_rlwnm_(self, RB, RS): n = RB[59:64] -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m return (RA,) - @inject() +@@ -45,7 +45,7 @@ def op_rlwimi(self, RS, RA): n = SH -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m | RA & ~m return (RA,) - @inject() +@@ -53,7 +53,7 @@ def op_rlwimi_(self, RS, RA): n = SH -- r = ROTL32(RS[32:64], n) + r = ROTL32(RS[32:64], n) - m = MASK(MB + 32, ME + 32) -+ r = ROTL32(EXTZ64(RS[32:64]), n) + m = MASK(MB.value + 32, ME.value + 32) RA = r & m | RA & ~m return (RA,) @@ -66,7 +59,7 @@ def op_slw(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], n) -+ r = ROTL32(EXTZ64(RS[32:64]), n.value) ++ r = ROTL32(RS[32:64], n.value) if eq(RB[58], 0): - m = MASK(32, 63 - n) + m = MASK(32, 63 - n.value) @@ -78,7 +71,7 @@ def op_slw_(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], n) -+ r = ROTL32(EXTZ64(RS[32:64]), n.value) ++ r = ROTL32(RS[32:64], n.value) if eq(RB[58], 0): - m = MASK(32, 63 - n) + m = MASK(32, 63 - n.value) @@ -90,7 +83,7 @@ def op_srw(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], 64 - n) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) if eq(RB[58], 0): - m = MASK(n + 32, 63) + m = MASK(n.value + 32, 63) @@ -102,7 +95,7 @@ def op_srw_(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], 64 - n) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) if eq(RB[58], 0): - m = MASK(n + 32, 63) + m = MASK(n.value + 32, 63) @@ -115,7 +108,7 @@ n = SH - r = ROTL32(RS[32:64], 64 - n) - m = MASK(n + 32, 63) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) + m = MASK(n.value + 32, 63) s = RS[32] RA = r & m | concat(s, repeat=64) & ~m @@ -126,7 +119,7 @@ n = SH - r = ROTL32(RS[32:64], 64 - n) - m = MASK(n + 32, 63) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) + m = MASK(n.value + 32, 63) s = RS[32] RA = r & m | concat(s, repeat=64) & ~m @@ -136,7 +129,7 @@ def op_sraw(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], 64 - n) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) if eq(RB[58], 0): - m = MASK(n + 32, 63) + m = MASK(n.value + 32, 63) @@ -148,7 +141,7 @@ def op_sraw_(self, RB, RS): n = RB[59:64] - r = ROTL32(RS[32:64], 64 - n) -+ r = ROTL32(EXTZ64(RS[32:64]), 64 - n.value) ++ r = ROTL32(RS[32:64], 64 - n.value) if eq(RB[58], 0): - m = MASK(n + 32, 63) + m = MASK(n.value + 32, 63) diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index a0381b9d..239e1d46 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -211,16 +211,16 @@ class DecoderTestCase(FHDLTestCase): initial_regs[1] = -1 with Program(lst) as program: sim = self.run_tst_program(program, initial_regs) - self.assertEqual(sim.gpr(3), SelectableInt(0xfe000fff, 64)) + self.assertEqual(sim.gpr(3), SelectableInt(0xfffffffffe000fff, 64)) def test_rlwimi(self): lst = ["rlwimi 3, 1, 5, 20, 6"] initial_regs = [0] * 32 - initial_regs[1] = 0xdeadbeef + initial_regs[1] = 0xffffffffdeadbeef initial_regs[3] = 0x12345678 with Program(lst) as program: sim = self.run_tst_program(program, initial_regs) - self.assertEqual(sim.gpr(3), SelectableInt(0xd4345dfb, 64)) + self.assertEqual(sim.gpr(3), SelectableInt(0xd5b7ddfbd4345dfb, 64)) def test_mtcrf(self): for i in range(4):