From: lkcl <lkcl@web>
Date: Sun, 8 Aug 2021 21:20:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~461
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3f1fe5499d39ba5673c8e1d8c3a22f0f0aca069c;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv/appendix.mdwn b/openpower/sv/int_fp_mv/appendix.mdwn
index 38a341ccf..3c256679f 100644
--- a/openpower/sv/int_fp_mv/appendix.mdwn
+++ b/openpower/sv/int_fp_mv/appendix.mdwn
@@ -64,7 +64,7 @@ would set the maximum to a Signed 16 bit integer.
 
 As always with SVP64, some thought and care has to be put into
 how the override behaviour will interact with the base scalar
-operstion.
+operation.
 
 # Equivalent OpenPower ISA v3.0 Assembly Language for FP -> Integer Conversion Modes